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STA450A
XMRADIO SDARS SERVICE LAYER & SOURCE DECODER
FUNCTIONS s XMRADIO SERVICE LAYER DEMULTIPLEXING
s s s s s s s s
CHANNEL AUXILIARY DATA MANAGEMENT CONDITIONAL ACCESS CONTROL SERVICE COMPONENTS EXTRACTION SERVICE COMPONENTS DECRYPTION HIGH QUALITY AUDIO DECODING WITH DATA RATE FROM 24kbps TO 96kbps HIGH QUALITY SPEECH DECODING WITH DATA RATE FROM 4kbps TO 16kbps 44.1 AND 32KHz SAMPLING FREQUENCIES SUPPORTED SYNCHRONIZATION ERROR DETECTION WITH SW INDICATORS
TQFP80 ORDERING NUMBER: STA450A
PERIPHERALS s HIGH SPEED SERIAL INPUT INTERFACE (PCBITSTREAM INTERFACE) s FULLY PROGRAMMABLE SERIAL PCM OUTPUT INTERFACE s IEC958 OUTPUT (S/PDIF) s DATA OUTPUT PORT INTERFACE s CONDITIONAL ACCESS PROCESSOR INTERFACE (I2C MASTER) s RS232 RX & TX INTERFACES s EMBEDDED SYSTEM PLL s EMBEDDED AUDIO PLL LOW POWER TECHNOLOGY s 1.8V 0.18m TECHNOLOGY s 3.3V CAPABLE I/Os CONTROL s I2C SLAVE CONTROL s DEVICE ADDRESS: 1011100
September 2003
(R)
T H I S D E V I C E C A N B E S O L D O N LY TO CUSTOMERS THAT HAVE SIGNED A LICENSE AGREEMENT WITH XM SATELLITE RADIO.
DESCRIPTION The STA450A is designed for digital radio receivers compatible with the XMRadio SDARS System and integrates all the functions needed to perform the Service Layer and Source Decoding: - Bitstream Synchronization - Service Layer (SL) Demultiplexing - Auxiliary Data Management - Conditional Access (CA) Control - Service Components Extraction - Service Components Decryption - Audio and Voice Decoding The extracted Audio and Data are made available through different interfaces: - I2S Audio Output - S/PDIF Output - Data Output Port
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STA450A
Figure 1. Service Layer and Source Decoder Block Diagram
1 LINE NU EVENT_IRQ INT1 INT2 7 LINES NU CAP_RST PLL_SYNC RS232_RX RS232_TX
TEST
SDA_M
SCL_M
I2C MASTER (CAP I/F)
I2C SLAVE (SYSCON I/F)
SDA
SCL
GPIO INTERFACE
RS232
EXTERNAL INTERRUPT
PCFS
SPDIFF OUTPUT
I958_OUT
PCDC PCSD
PC BITSTREAM INPUT INTERFACE (USSIO 0)
INPUT BUFFER
SERVICE LAYER DEMUX
DECRYPTION
AUDIO DECODER
OUTPUT BUFFER
AUDIO PORT OUTPUT INTERFACE (PCM I/F)
SDO SCKT LRCKT
DSP BASED SYSTEM & AUDIO CLOCKS
OCLK DP_CLK DP_DATA DP_EN
DATA PORT OUTPUT INTERFACE (USSIO 3) AUDIO PLL
SYS PLL
RESET_N
CLK_OUT
CLK_IN
Figure 2. Pin Connection
TEST (GPIO_3)
FILT_0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NU (IT_1) GND1 VDD1 TEST0 CLK_IN NU (IT_2) TESTB CAP_RST (GPIO_4) GND2 VDD2 VDD_IO1 CLK_OUT SCL_M SDA_M GND3 VDD3 NU (FIT_0) SCAN_MODE APLL_GND APLL_VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PLL_SYNC (FIT_5)
NU (USSIO0_LRCLK)
GND10
INT1 (GPIO_1)
I958_OUT
DP_DATA
DP_CLK
DP_EN
INT2 (GPIO_2)
RS232_RX
RS232_TX
GND12
LRCKT
VDD_IO4
GND11
VDD12
VDD10
VDD11
OCLK
SCKT
SDO
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SDA SCL VDD9 GND9
EVENT_IRQ (GPIO_0)
RESET_N TEST1 NU (IT_0) VDD_IO3 VDD8 GND8 NU (GPIO_5)
NU (USSIO2_SCLK) NU (USSIO2_DATA) NU (USSIO2_LRCLK)
VDD7 GND7
NU (USSIO1_SCLK) NU (USSIO1_DATA) NU (USSIO1_LRCLK)
FILT_0
PCFS (FIT_2)
NU (FIT_3)
NU (FIT_4)
NU (FIT_1)
CLK_M1
NU
VDD4
VDD_IO2
CLK_M0
PCDC
GND6
GND4
GND5
VDD5
NU (REQ)
PCSD
VDD6
TQFP80
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STA450A
PIN FUNCTION
N 1,6,53 Pin NU(IT_1), NU(IT_2), NU(IT_0) GND1...,GND12 Type I Function Not Used (must be connected to ground in functional mode) Ground Pad Description Schmitt Trigger Buffer
2,9,15,23, 30,37,44,5 0,57,62,69 ,76 3,10,16, 24,31,38,4 5,51,58,63 ,70,77 4 5 7 8 11,32,52,7 1 12 13 14 17,27,28,4 0 18 19 20 21 22 25,26 29 33 34 35,41,46
VDD1...,VDD12
1.8V Core Supply Voltage
TEST0 CLK_IN TESTB CAP_RST (GPIO_4) VDD_IO1,... VDD_IO4 CLK_OUT SCL_M SDA_M NU(FIT_0), NU(FIT_3), NU(FIT_4), NU(FIT_1) SCAN_MODE APLL_GND APLL_VDD FILT_0 NU CLK_M1, CLK_M0 PLL_SYNC (FIT_5) PCDC PCSD NU(USSIO0_LRCLK) NU(USSIO1_LRCLK) NU(USSIO2_LRCLK) NU(REQ)
I I I I/O
Test Pin (must be connected to ground in functional mode) Clock Input Test Pin CAP Reset 3.3V I/O Supply Voltage
Analog Pad Schmitt Trigger Buffer Input Pad Buffer with Active Pull-Up Bi Dir Pad, 4mA Output Buffer with Slew Rate Control
O O I/O I
Clock Out I2C Master Serial Clock I2C Master Serial Data Not Used (must be connected to ground in functional mode) Scan Mode (must be connected to ground in functional mode) Analog Ground for Audio PLL 1.8V Analog Supply for Audio PLL PLL Filter Not Used
4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Buffer
I
Input Pad Buffer
Analog Pad
I I I/O I/O I/O
Selection of Input Clock for the DSP Input Pad Buffer core and peripherals Fractional Audio PLL Sync. PC Bitstream Data Clock PC Bitstream Serial Data Not Used (must be connected to ground in functional mode) Not used Schmitt Trigger Buffer Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control
36
O
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STA450A
PIN FUNCTION (continued)
N 39 42,47 43,48 49 54 55 56 59 60 61 64 65 66 67 68 72 73 74 75 78 79 80 Pin PCFS(FIT_2) NU(USSIO1_DATA) NU(USSIO2_DATA) NU(USSIO1_SCLK) NU(USSIO2_SCLK) NU(GPIO_5) TEST1 RESET_N EVENT_IRQ (GPIO_0) SCL SDA INT1 (GPIO_1) INT2 (GPIO_2) TEST (GPIO_3) DP_EN DP_DATA DP_CLK LRCKT SDO SCKT OCLK I958_OUT RS232_TX RS232_RX Type I I/O I/O I/O I I I/O I I/O I/O I/O I/O I/O I/O I/O O O O I/O O O I Function PC Bitstream PRC Frame Sync. Not Used (must be connected to ground in functional mode) Not Used (must be connected to ground in functional mode) Not Used (must be connected to ground in functional mode) Test Pin HW Reset (active low) General Interrupt (Events, Errors, Data ready) I2C Slave Serial Clock I2C Slave Serial Data Dedicated Errors Interrupt Dedicates Events Interrupt Test Pin Data Port Enable Data Port Data Data Port Clock I2S Left&Right Clock I2S Output Data (PCM Data) I2S Serial Clock Oversampling Clock S/PDIF Output RS232 Transmitter RS232 Receiver (must be connected to ground in functional mode) Pad Description Schmitt Trigger Buffer Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Input Pad Buffer with Active Pull-Up Schmitt Trigger Buffer Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Buffer BiDir Pad, 4mA Output Buffer with Slew Rate Control Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control Schmitt Trigger Bi Dir Pad, 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control Schmitt Trigger BiDir Pad, 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control 4mA Output Buffer with Slew Rate Control Schmitt Trigger Buffer
A more detailed description of each pad type can be found in section 4.
Note: After an Hardware reset or power on all Bi Dir pins are configured as inputs.
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STA450A
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDD_IO APLL_VDD Vi Vo Tstg Toper Tj 1.8V Power supply Voltage 3.3V Power Supply Voltage 1.8V Analog Supply Voltage Voltage on input pin Voltage on output pin Storage temperature Operative Ambient Temperature Operative Junction Temperature Parameter Value -0.5 to 2.5 -0.5 to 4 -0.5 to 2.5 -0.5 to (VDD_IO + 0.5) -0.5 to (VDD_IO + 0.5) -55 to +150 -40 to +85 -40 to +125 Unit V V V V V C C C
THERMAL DATA
Symbol Rj-amb Parameter Thermal Resistance Junction to Ambient (1) Value 40 Unit C/W
(1) According to JEDEC specification on a 4 layers board
DC ELECTRICAL CHARACTERISTCS (Tamb = -40 to 85C, VDD = APLL_VDD = 1.65 to 1.95V, VDD_IO = 3.0 to 3.6V unless otherwise specified).
Symbol VDD VDD_IO APLL_VDD IDD IDD_IO Parameter 1.8V Supply Voltage 3.3V Supply Voltage 1.8V Analog Supply Voltage VDD Power Supply Current VDD_IO Power Supply Current fCLK = 23.92MHz; 56kbps audio stream; VDD=1.95V fCLK = 23.92MHz; 56kbps audio stream; VDD_IO=3.6V; VDD=1.95V fCLK = 23.92MHz; APLL_VDD =1.95V VDD = 1.8V; VDD_IO = 3.3V
4)
Conditions
Min 1.65 3.0 1.65
Typ 1.8 3.3 1.8 110 24
Max 1.95 3.6 1.95 140 40
Unit V V V mA mA
IDD_APLL PD Iil Iih IOZ Ipu Rpu Vil Vih Vilhyst Vihhyst Vhyst
APLL_VDD Power Supply Current Power Dissipation Low level input leakage current
0.5 220
1.2
mA mW
Vi = 0V Vi = VDD3 Vo = 0V or VDD3 Vi = 0V 40 50
1 1 1 120
A A A A k
High level input leakage current 4) Tristare output leakage current 5) Pull-up current Equivalent pull-up resistance Low level input voltage High level input voltage Low level threshold input falling High level threshold input rising Schmitt trigger hysteresy
1) 3)
Vi = 0V
0.8 2 0.8 1.3 0.3 1.35 2 0.8
V V V V V
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STA450A
DC ELECTRICAL CHARACTERISTCS (continued)
Symbol Vol Voh CIN COUT CIO Ilatchup VESD Parameter Low level output voltage
2)
Conditions Iol = 4mA Ioh = 4mA
Min
Typ
Max 0.2
Unit V V
High level output voltage 2) Input Capacitance
1)
2.8 1.2 1.9 2.1 200
pF pF pF mA V
Output Capacitance 1) I/O (BiDir) Capacitance 1) I/O Latching Current Electrostatic Protection Leakage<1A 4000
Note 1. Guaranteed by Design Note 2. Take into account 200 mV voltage drop in supply lines and Input/Output levels for frequency > 20MHz. Note 3. Guaranteed by Ipu measurements Note 4: Performed on all the input pins excluded the pull-down ones Note 5: Performed on the I/O pins in tristate mode
1.0 FUNCTIONAL DESCRIPTION 1.1 PC BITSTREAM INTERFACE The STA450A receives a serial data stream from the STA400A Channel Decoder via the PC Bitstream Interface. Figure 3 shows the stream format outputs from the CDEC (STA400A). Figure 3. PC Bitstream Interface protocol
432ms frame period
PCSD
TSCC1
TSCC2
PRC_A1
PRC_An PRC_B1 CLOCK
PRC_Bn
PRC_Z1
PRC_Zn
PCDC PCFS
PCSD
PCDC PCFS
Table 1 shows the correspondence between CDEC output clock divider register and the data rate on the bus
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STA450A
Table 1. Suggested CDEC clock divider/output rate correspondence.
MCLK (Hz) 23920000 Divider 2 4 6 8 F Out (Hz) 11960000 5980000 3986667 2990000 T Out (sec) 8.361E-08 1.672E-07 2.508E-07 3.344E-07 T Burst (sec) 2.997E-04 5.993E-04 8.990E-04 1.199E-03
The 432ms frame is divided in slots of 448 bytes; the minimum number af slots in a 432ms frame is 50, corresponding to a Tslot of 8.64ms. The transmission is on bursts, whose duration can go from 299us up to 1.199ms (refer to table 1) according to the clock divider factor selected in the STA400A. An overview of the connection between the STA400A and the STA450A is given in Figure 4.
Figure 4. STA400A/STA450A Connection.
DSP
HEADER BUFFER DECRYPT BUFFER
PCSD - DATA LINE
TX/RX
USSIO
PCDC - CLOCK LINE CDEC
SCLK
SERVICE LAYER PC BUFFER
AUDIO BUFFER
PCFS
FAST IT
DATA BUFFER
MFP -PLL SYNC
FAST IT
The synchronization process is started after a PCFS pulse is received through a Fast Interrupt port (pin 39). In the case the PC Bitstream is stopped or the clock line is perturbed, the PCFS signal is used to reset the firmware State Machine in the PC Bitsteam Interface (STA450A); this mechanism guarantees the start of the resync process from a stable state. The PC Bitstream Interface receives the data and fills the Header and the PC buffers; the Header buffer contains the Header byte 1, the Header byte 2 and the Service preamble, the PC buffer contains the Payload channels data.
1.2 STA450A Clocks Generation System The STA450A Clocks generation System is shown in Figure 5: the 23.92MHz reference signal is entered in the pin CLK_IN and is used to generate an internal system clock, with a System PLL, and an internal PCM clock, with an Audio Fractional PLL . A clock is made available at the output through the pin CLK_OUT.
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STA450A
Figure 5. STA450A Clocks Generation System
CLKOUT
sys_paddiv(3:0) FREF CLK_IN DIV MD+1 FIN PFD CHARGE PUMP R C3 C VCO /2
/2 (N+1)
MMDSP + CORE
MMIO PERIPHERALS
Emulation Unit GPIO RS232 Interfaces I2C master Host Interface IO ROM Timers Ext Interrupt IT remap
PLL DISABLE DIV MD+1
sys_clk /2
m4
FRAC0 SWITCHING CIRCUIT DIV MD+1 sys_clockout
PCM INTERFACE
sysclk SYSTEM PLL
USSIO0
external filter FREF DIV MD+1 FIN PFD CHARGE PUMP R C3 C VCO
sysclk
USSIO1
PLL DISABLE DIV MD+1
sysclk
USSIO2
sysclk SWITCHING CIRCUIT DIV MD+1 audio_clockout
USSIO3
FRAC0
audio sample counter AUDIO PLL OCLK internal_pcmclk
D02AU1415
m5
The system clock The system clock sent to the DSP core and the peripherals can be derived from 4 sources of clock and the selection is performed by m4. The control of m4 is performed by the 2 input pins (CLK_M1 & CLK_M0): - 00 sys_clk = CLK_IN - 01 sys_clk = CLK_IN divided by 2 - 10 sys_clk = sys_clockout - 11sys_clk = sys_clockout divided by 2 In the chip, the duty cycle of the internal system clock must be as close as possible 50%. When the sys_clk is derived from the external clock source (CLK_IN), the divider by 2 can be used to ensure a 50% duty cycle. When the sys_clk is derived from the system PLL, the duty cycle of the sys_clockout signal is 50%. The divider by 2 can be used to slow down the clock at a lower frequency than the minimum that can achieve the System PLL. The CLK_OUT pad is driven by the sys_clk divided by a programmable division factor ranging from 1 to 16; the sys_clk frequency is divided by 2 * (N+1), where N is the value programmed with register sys_paddiv [3:0]. Configuration Equations for the System PLL:

Fref IN 1 reference Fout = ------------- ---------------- M + 1 + ---------------------------X+1 N+1 65536
X = pllsys_Xmodulo
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STA450A
N = pllsys_Nmodulo M = pllsys_Mmodulo The System PLL registers are configured through an indirection mechanism using the HOST_pll_add, HOST_pll_data and HOST_pll_cmd registers; the HOST_pll_cmd register allows to update the control registers of the PLL. There are two levels of registers (Level 1 & Level 2). The first level of registers (Level 1) is configured through the indirection mechanism. The second level of registers (Level 2) is a copy of the previous level in order to update all the configuration bits at the same time. This mechanism avoids to have, during the configuration phase, intermediate configurations that are not in line with the final desired configuration. Assuming a 23.92MHz CLK input frequncy and CLK_M[1:0] = "11", the default system frequency is 59.8MHz See also the register description. The Audio PLL The "internal_pcmclk" of STA450A can be provided by two different sources: the Audio PLL or the OCLK port of the chip. The "m5" multiplexor and the direction of the OCLK tri-state port are configured by the register HOST_Pllpcm (address 0x12). An Audio PLL is embedded in STA450A. The particularity of STA450A Audio PLL is the possibility to modify the Audio Sampling Frequency (LRCKT) in steps of a few p.p.m. to compensate dynamically the audio sampling frequency offset between the receiver and the broadcasting station; this compensation produces a jittering effect outside the audible range. The STA450A receives from the STA400A (Channel Decoder) a dedicated signal every 432ms (PLL_SYNC) and uses this signal to perform the audio sampling rate compensation; the control is done by the DSP core updating the internal PLL registers. Some PLL configuration registers are made available to the user to configure the PCM output according to the used DAC.
The programmation for the desired Fs should be accomplished for both the Fs = 48KHz and Fs = 44.1KHz families before the start-up of the DSP (write in the register 0 x 4D) The OCLK frequency can be derived from the following formula:

1 - 23.92MHz OCLK_freq = ------------ ---------------------------- M + 1 + FRAC ----------------1+X 1+N 65536

- X is the value of the HOST_APLL48_XDIV register (HOST_APLL441_XDIV) register. - M is the value of the HOST_APLL48_MDIV register (HOST_APLL441_MDIV) register. - N is the value of the HOST_APLL48_NDIV register (HOST_APLL441_NDIV) register. - FRAC is the decimal value of the concatenated registers HOST_APLL48_LSB and HOST_APLL48_MSB (HOST_APLL441_LSB and HOST_APLL441_MSB) as follows: FRAC = 256 * HOST_APLL48_MSB + HOST_APLL48_LSB (= 256 * HOST_APLL441_MSB + HOST_APLL441_LSB) The changes in the registers are not effective once the DSP has been started.
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STA450A
According to the chosen oversampling factor, the following table permits to configure the dividers of the Audio PLL:
O_FAC Fs=48KHz family 256 384 512 Fs=44.1KHz family 256 384 (default) 512 1 1 1 15 14 15 64948 37691 64948 17 10 8 1 1 1 15 14 15 28756 26959 28756 15 9 7 N M FRAC X
See also the register description.
1.3 PCM Output Interface The decoded audio data can be output in serial PCM format. The interface consists of the following signals: SDO PCM Serial data output SCKT PCM serial Clock Output LRCKT Left/Right Channel Selection Clock The output samples precision is selectable from 16 to 24 bits/word by setting the output precision (16, 18, 20 and 24bits) with the HOST_PCMCNF register; the same register is used to output data either with the most significant bit first (MS) or least significant bit first (LS). Figure 6 gives a description of the STA450A PCM Output Formats. The SCKT signal is the bit clock for the serial output and is derived from the PCMCLK (OCLK) as in the following formula: SCKT = OCLK / 2*(HOST_PCMDIV + 1) The number of bits to be transmitted to the DAC during one LRCKT clock period depends on the DAC precision (16, 18, 20 or 24bits) and on the mode used to transmit the data (LRCKT_period equal to 16x2 or 32x2 SCKT_period - refer to figure 6). The value of the HOST_PCMDIV register must be set accordingly to the previous consideration and to the DAC Oversampling Factor (O_FAC). - LRCKT_period = 16x2 SCKT_period HOST_PCMDIV = (O_FAC/64) - 1 - LRCKT_period = 32x2 SCKT_period HOST_PCMDIV = (O_FAC/128) - 1 See also the register description.
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W : R/W BIT = WR IT E SA : SLA VE ACK NO WL ED GE @ : SUB -AD DRE SS V AL UE STAR T STAR T STAR T D AT A T O @+1 SLA VE A DD RESS SLA VE A DD RESS SLA VE A DD RESS SA DA TA TO @+2 SA
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M S L S M L S 18, 20 o r 24 b its S M 0 S 18, 20 o r 24 b its 16 sc lk cyc les
MS B
a) Write sequences
The I2C master interface is used by the STA450A to communicate with the external Conditional Access Processor (CAP) with the following protocol:
1.4 Master Interface I2C
Figure 6. PCM Output Formats
PC M_OU T[2:0]
PC M_OU T[2:0]
LR CLK
PC M_OU T[2:0]
PC M_OU T[2:0]
PC M_OU T[2:0]
PC M_OU T[2:0]
LRC LK
0
32 s clk c yc les
M L S 18, 20 or 24 bits S
M L S 18, 20 o r 24 b its S
M S
LM SS
L S
16 sc lk cyc les
L S
0
S UB-A D DR ES S IN ITIALIZATION
SU B-ADD RES S + MU LTIP LE W RITE
S UB-A DDRES S + S ING LE W RITE
W
W
W
0
M S
L S
SA
SA
SA
L M 0 S 18, 20 o r 24 b its S
M L S 18, 20 or 24 bits S
SUB-AD DRE SS @
SUB-AD DRE SS @
SUB-AD DRE SS @
MS B
0
32 sc lk cy cles
M L S 18, 20 o r 24 b its S
M L S 18, 20 or 24 bits S
STO P
PC M_OR D = 0, PC M_PR EC is 16 bits mode
PC M_OR D = 1, PC M_PR EC is 16 bits mode
SA STO P
SA
SA
0
D AT A TO @ SA
D AT A TO @ SA ST OP
0
PC M_FO R MA T = 1 PC M_DIFF = 0
PC M_FO R MA T = 0 PC M_DIFF = 1
PC M_FO R MA T = 0 PC M_DIFF = 0
PC M_FO R MA T = 1 PC M_DIFF = 1
STA450A
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b) Read sequences
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STA RT STA RT R : R/W BIT = REA D SA : SLA VE A CKN OW LE DG E MA : M AST ER ACK NO WL ED GE NM A : N O M AST ER A CKN OW LE DG E (LA ST D AT A) @ : SUB-A DD RESS V AL UE ST ART DA TA FROM @ + 1 N M A SL AVE A DD RESS SLA VE AD DRE SS SL AV E AD DRE SS ST ART
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The SPDIF output is a Fully IEC958 formatted, single ended output for linear PCM output (left and right channel, 16,18, 20 & 24 bits) supporting the Consumer Mode. 1.6 IEC958 Output (SPDIF) Figure 7. Data Port Protocol Waveform Diagram The Data Port burst rate is selectable through the XM Stack Command DATAPORT_CH_FREQUENCY (opcode 0x07) from 1 MHz to 12 MHz, the default rate is 2 MHz. The Service Component is output through the Data Port without adding a flag indicating the frame. The data changes on the DP_DATA line on the raising edge of the clock line DP_CLK, the DP_EN line defines when the data is valid; DP_DATA and DP_EN must be sampled on the falling edge of DP_CLK. The STA450A sends data through the Data Port. The Data Port consists of 3 lines: DP_CLK, DP_DATA, DP_EN. The communication protocol is in burst. 1.5 Data Output Port
STA450A
DP_DATA
DP_CLK
DP_EN
C OMBIN ED F OR MA T : SU B-A DD R ESS + S IN GLE R EAD
CO MBINED FO RM AT : SU B-AD D RES S + M ULTIPLE R EA D
SLA VE AD W W WSA ST OP SA R SU B-AD DRE SS @ SA R SA
M ULTIPLE R EA D
SU B-AD DRE SS SA STAR
S ING LE REA D
FIRST DA TA
SA STA RT D AT A
SLA VE AD -
MA
SL AV E AD DRE SS N M A STO P
SECO ND DA TA
R SA
R
SA
D AT A FROM @ N M A STO P
DA TA FRO M @ M A NM A ST OP
STA450A
1.7 Test Interfaces (RS232) The STA450A provides a RS232 RX and a RS232TX interfaces for testing purposes.
2.0 I2C BUS SPECIFICATION The STA450A supports the I2C protocol to communicate with the System Controller; the STA450A is always a slave in its communication to the System Controller.
2.1 COMMUNICATION PROTOCOL A data change on the SDA line must only occur when SCLKI2C clock is low except for START and STOP conditions. In that case, the transition is done when the clock is High. A START condition is identified by a High to Low transition of the SDA line while the clock signal is High. A START condition must precede any command for a data transfer. A STOP condition is identified by a Low to High transition of the SDA line while the clock signal SCLKI2C is High. A STOP condition terminates the communications between the IC and the master of the I2C bus. An Acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either the master or the slave, releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA line to Low to acknowledge the reception of 8 bits of data. During the data transfer, the I2C slave interface of the IC samples the SDA line on the rising edge of the SCLKI2C clock. The SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCLKI2C clock line is low.
2.2 DEVICE ADDRESSING To start the communications between the master and the IC, the master must initiate the transfer with a START condition. Then, the master has to send on the SDA line 8 bits (MSB first) corresponding to the device I2C address (7 bits) and the mode bit RW (Read or Write). The 7 most significant bits are the address of the device. For the STA450A the address is 0x5C (1011100 address on 7 bits). The 8th bit (LSB) selects a read (bit set to 1) or write (bit set to 0) operation. After a START condition, the IC I2C slave interface identifies on the I2C bus the device address and, if the address matches, the IC acknowledges this match on the SDA line during the 9th bit time frame. The byte following the device identification byte is the address of the Host register to be accessed. 2.2.1 Sub-address initialization
This mode is used for the initialization of the Host address register (sub-address value). The Host address register is the register that points the data register to be accessed (read or write).
2.2.2
"Sub-address + single write" & "Sub-address + multiple write"
The second mode, the multiple write, exploits the autoincrementation of the sub-address pointer to avoid to initialize, for sequential accesses of the Host registers, the sub-address at each write operation. The length of a multiple write is limited to the size of the Host register area (256 locations). After a writing in the I2C interface a interrupt is generated to the core if the System controller set the bit in the HOST_Cmd0 register.
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The multiple read operations are performed from the current sub-address value and the sub-address register is automatically incremented at each access. The sub-address value can be initialized using the "sub_address initialization" sequence presented in the previous transfer chart : see the "combined format - sub-address + multiple read" diagram in the following chart. The length of a multiple read is limited to the size of the Host register area (256 locations). A multiple read is terminated by a Non Master Acknowledge followed by a STOP condition.
ST ART ST ART STA RT D AT A FRO M @ + 1 NMA SL AV E AD DRE SS SLAV E A DD RESS SL AV E A DD RESS STA RT
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STA450A
W : R/W BIT = WRIT E SA : SLA VE ACK NO WL ED GE @ : SUB-AD DRE SS V AL UE START START START D AT A T O @+1 SLA VE A DD RESS SLA VE A DD RESS SLA VE A DD RESS SA DA TA TO @+2 SA
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The single read operations are performed from the current sub-address value. The sub-address value can be initialized using the "sub_address" initialization" sequence presented in the previous transfer chart : see the "combined format - sub-address + single read" diagram in the following chart.
2.2.3
"Single read" & "multiple read" & "sub-address + single read" & "sub-address + multiple read"
C OM BIN ED FOR MA T : SUB-A D DR ESS + SIN GLE REA D
C OMBIN ED FO RM AT : SU B-AD D RESS + MU LTIPLE REA D
SLA VE A DW W WSA STO P SA R SUB-A DD RESS @ SUB-A DD RESS SA
R : R/W BIT = RE AD SA : SLA VE ACK NO WL ED GE MA : M AST ER A CKN OW LE DG E N M A : N O M A STE R ACK NO WL ED GE (L AST DA TA ) @ : SU B-AD DRE SS VA LU E
MU LTIP LE REA D
SIN GLE R EAD
R
SA
S UB-A D DR ESS IN ITIA LIZA TION
SU B-AD D RES S + MU LTIP LE W RITE
SUB-A D DR ESS + SING LE W RITE
W
W
W
FIRST DATA
SA
SA
SA
SA ST AR
SA ST ART DA TA
SUB-AD DRE SS @
SUB-AD DRE SS @
SUB-AD DRE SS @
SL AV E A D-
SLA VE A DDRE SS MA
STO P
N MA ST OP
SE CON D DA TA
SA
SA
SA
R SA
R
STO P
D AT A TO @ SA
D AT A TO @ SA ST OP
SA
D AT A FROM @ NMA ST OP
D AT A FROM @ MA NMA ST OP
STA450A
2.3 REGISTER MAP The DSP HOST interface includes 256 registers.
HOST @ 0x00 0x01 0x02 to 0x0F 0x10 0x11 0x12 0x13 0x14 to 0x17 0x18 0x19 to 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 to 0x2A 0x2B 0x2C to 0x39 0x3A 0x3B to 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 Name HOST_VERSION HOST_ID Reserved HOST_SOFTRESET HOST_Plldata HOST_Pllpcm HOST_cmd0 Reserved HOST_Pllcmd Reserved HOST_I2cdiv HOST_Plladd HOST_SerialDivL HOST_SerialDivH Reserved Host_Memory Access Reserved Host_clkstop Reserved HOST_SOFTVER HOST_EVENTINTE0 HOST_EVENTINTE1 HOST_EVENTINTE2 HOST_EVENTINTE3 HOST_EVENTINT0 HOST_EVENTINT1 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits R-W R-W R-W R-W R-W R-W R-W NA NA NA NA NA NA NA NA NA NA NA NA NA NA Software version (BCD) EVENT Interrupt enable bit[7:0] EVENT Interrupt enable bit[15:8] EVENT Interrupt enable bit[23:16] EVENT Interrupt enable bit[31:24] EVENT Interrupt value bit[7:0] EVENT Interrupt value bit[15:8] 1bit W NA 1 Stops the clock to the core 4 bits W 0x00 0x00 Enables core to access ucode 6 bits 8 bits 8 bits 8 bits R-W R-W R-W R-W 0x0B NC 0x00 0x00 0x0B 0 0x00 0x00 Hold time value of the data on SDA versus SCL edges Address register to configure the different configuration registers RS232 rate coeff L RS232 rate coeff H 8 bits R-W NC 0 Command register to configure the PLLs 8 bits 8 bits 3 bits 1 bit W R-W R-W R-W NA NC NC 0 NA 0 01 0 Soft reset of the DSP core and peripherals Data register to configure the different configuration registers PCM clock direction configuration I2C Interrupt request Register size 8 bits 8 bits Mode R R SW Reset 0x10 0x20 HW Reset 0x10 0x20 Comment
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STA450A
Register size 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits SW Reset NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA HW Reset NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
HOST @ 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 to 0x65 0x66
Name HOST_EVENTINT2 HOST_EVENTINT3 HOST_ERRINTEL HOST_ERRINTEH HOST_ERRINTL HOST_ERRINTH HOST_STARTUP HOST_PCMDIV HOST_PCMCNF HOST_APLL48_LSB (1) HOST_APLL48_MSB(1) HOST_APLL48_XDIV(1) HOST_APLL48_MDIV(1) HOST_APLL48_NDIV(1) HOST_APLL441_LSB(1) HOST_APLL441_MSB(1) HOST_APLL441_XDIV(1) HOST_APLL441_MDIV(1) HOST_APLL441_NDIV(1) ENABLE_IT432 IT432_CONF HOST_MaxDev HOST_Decoder BitRate HOST_Bitstream Synchro Host_DataPort_BitRate Reserved HOST_EVENTINTE4
Mode R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W R-W
Comment EVENT Interrupt value bit[23:16] EVENT Interrupt value bit[31:24] ERROR Interrupt enable bit[7:0] ERROR Interrupt enable bit[15:8] ERROR Interrupt value bit[7:0] ERROR Interrupt value bit[15:8] Startup Pcm clock divider Pcm Configuration Fractional PLL LSB reference value for Fs = 48KHz family Fractional PLL MSB reference value for Fs = 48KHz family Fractional PLL X Divider for Fs = 48KHz family Fractional PLL M Divider for Fs = 48KHz family Fractional PLL N Divider for Fs = 48KHz family Fractional PLL LSB reference value for Fs = 44.1KHz family Fractional PLL MSB reference value for Fs = 44.1KHz family Fractional PLL X Divider for Fs = 44.1KHz family Fractional PLL M Divider for Fs = 44.1KHz family Fractional PLL N Divider for Fs = 44.1KHz family Enable control with FRAC PLL Edge configuration for IT432 Hax duration windows divider factor Active Audio decoder bitrate Synchronization Data Port Bit Rate
8 bits
R-W
NA
NA
EVENT interrupt enable bit [7:0]
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STA450A
Register size 8 bits 8 bits 8 bits SW Reset NA NA NA HW Reset NA NA NA
HOST @ 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D to 0x7E 0x7F 0x80 to 0xFF
Name HOST_EVENTINTE5 HOST_EVENTINT4 HOST_EVENTINT5 Reserved AudioDec Result HOST_MFC Command HOST_PAGE_CTRL Data Page
Mode R-W R-W R-W
Comment EVENT interrupt enable bit [15:8] EVENT interrupt value bit [7:8] EVENT interrupt value bit [15:8]
8 bits 8 bits 8 bits 8 bits 8 bits
R-W R-W R-W R-W R-W
NA NA NA NA NA
NA NA NA NA NA
Audio Decoder Result Master Frame counter (MFC) LSB part (7 bits)
More page indication and number of byte in the page
Note: NA: Not Applicable, NC: Not Change, R: Read Only, W: Write Only Note1: These registers must be programmed before the start-up of the DSP (writing in register 0x4D)
2.4 REGISTER DESCRIPTION HOST_VERSION
7 00 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x00 :R : 0x10 : 0x10
Description The VERSION register is read-only and is used to identify the IC cut . The VERSION register holds the cut number (binary decimal encoded)
HOST_ID
7 01 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x01 :R : 0x20 : 0x20
Description The HOST_ID register is read-only and is used to identify the IC on an application board. The ID is fixed for all IC cut. The STA450A has the ID 0xAC.
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STA450A
HOST_SOFTRESET
7 10 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x10 :W : NA : NA
Description When bit 0 of this register is set, a soft reset occurs. The command registers and the interrupt registers are cleared. The STA450A goes into idle mode.
HOST_Pllpcm
7 12 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset Description 00 Not used 01 10 11
: 0x12 :R-W : NC : 0x01
The PCMCLK pad is in input. This external PCMCLK source is sent to the I2S PCM output. The PCMCLK pad is in output. The internal audio PLL is generating the PCM clock for the I2S PCM output. Same case as 10 but the PCMCLK is in tri-state mode
HOST_Plldata
7 11 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x11 : R/W :0 :0
Description Data to be copied in the Level 1 register for system PLL. This register should be used in conjunction with registers HOST_Pllcmd and HOST_Plladd
HOST_Pllcmd
7 18 6 5 4 3 2 1 0
Address Type Software Reset
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: 0x18 : R/W :0
STA450A
Hardware Reset :0
Description Bit [1:0] 00: no action is performed on the configuration registers of the Level 1. 01: Read action of the configuration registers. During this phase, the content of a selected (by HOST_pll_add) configuration register of the Level 1 is copied into the HOST_pll_data register. 10: Write action of the configuration registers. During this phase, the content of the HOST_pll_data register is copied into a selected (by HOST_pll_add) configuration register of the Level 1. 11: do not use. Bit 2 The bit controls the transfer of the data between the Level 1 and the Level 2 for the System PLL. When this bit is set, all the registers of the Level 1 (sys_ndiv, sys_pdiv, sys_setupH, sys_setupL, sys_enable) are copied into the registers of the Level 2 at the same time. When this bit is cleared, all the Level 2 registers have a stable state independently of the Level 1 registers. Bit3 Reserved Bit 4 This bit must be used when switching from one System PLL configuration to the other one. This bit must be used in conjunction with the bit [2].
HOST_Plladd
7 1D 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x1D : R/W :0 :0
Description
In the follow table the description of the registers addressable by the HOST_Plladd to control the system PLL
Add 3 Name pllsys_disable Size 1 Mode R-W SW Reset NC HW Reset 0 Comment System PLL disable control 0 : system PLL enabled 1 : system PLL disabled 8 low bits of Fractional value for system PLL 8 high bits of Fractional value for system PLL S divider for system PLL N divider for system PLL X divider for system PLL M divider for system PLL Update Fractional value for system PLL pad clock divider
4 5 6 7 8 9 10(0xA) 12(0xC)
pllsys_F_low pllsys_F_high pllsys_S pllsys_N pllsys_X pllsys_M pllsys_update_frac pllsys_paddiv
8 8 5 4 7 5 1 4
R-W R-W R-W R-W R-W R-W R-W R-W
NC NC NC NC NC NC NC NC
0 0 2 1 0 9 0 3
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STA450A
HOST_Cmd0
7 13 6 5 4 3 2 1 0 Cmd0
Address : 0x13 Type : R/W Software Reset :0 Hardware Reset :0 Description A write into the bits 0 of this register generates a interrupt to the DSP core
HOST_I2cdiv
7 1C 6 5 4 3 Div [5:0] 2 1 0
Address : 0x1C Type : R/W Software Reset : 0x0B Hardware Reset : 0x0B Description Hold time = HOST_I2cdiv/fc where the fc is the DSP system frequency. HOST_SerialDivH - HOST_SerialDivL
7 1F 1E 6 5 4 Div [15:8] Div[7;0] 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x1F - 0x1E : R/W : 0x00(HOST_SerialDivH) - 0x00 (HOST_SerialDivL) : 0x00 (HOST_SerialDivH) - 0x00 (HOST_SerialDivL)
Description These registers are used to specify the frequency division factor of the system clock for the RS232 interface used for the emulation; bit rate = fc/(( HOST_SerialDivH << 8) | HOST_SerialDivL)
HOST_MemoryAccess
7 2B 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x2B :W : NA :0
Description Setting the bit 3 the core is enabled to access the ucode inside the memory
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STA450A
HOST_ClkStop
7 3A 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x3A :R : NA :0
Description Clearing the bit 0 the clock to the core is started.
HOST_SOFTVER
7 40 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x40 : R/W : NA : NA
Description The SOFTVER register is the version of the microcode which is running on the device (BCD). This register is updated just after a soft reset of the device.
HOST_EVENTINTE 0 -1 -2 -3
7 44 43 42 41 6 5 4 3 2 1 0
INTE[31:24] INTE[23:16] INTE[15:8] INTE[7:0] : 0x44 - 0x41 : R/W : NA : NA
Address Type Software Reset Hardware Reset
Description These registers are associated to error condition inside the STA450A. The STA450A contains a 32 bits interrupt register associated with 32 bits enable register. A bit set in this register will enable the generation of an external interrupt on the interrupt line. The interrupt associated with each bit is given in the register INT description.
HOST_EVENTINT 0 - 1 - 2 - 3
7 48 47 46 45 6 5 4 3 2 1 0
INT[31:24] INT[23:16] INT[15:8] INT[7:0]
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STA450A
Address Type Software Reset Hardware Reset : 0x48 - 0x45 : R/W : NA : NA
Description These registers are associated to error condition inside the STA450A.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding bit in the INTE table has been set an external interrupt is generated. To clear the bit a fast command has to be issued (see command description).
Name BAC_Authorization BAC_Deauthorization UTC Response CRB_Table_Complete BIC_ServiceLabel_0 BIC_ProgramTypeLabel_0 BIC_ServiceSelection_0 BIC_SongArtistLabel_0 BIC_ChannelRefernceLabel_0 ADF_ExtArtistLabel_0 ADF_ExtSongLabel_0 ADF_Text_0 ADF_ProgramStart_0 ADF_ProgramEnd_0 ADF_ProgramId_0 ADF_Other_0 BIC_ServiceLabel_1 BIC_ProgramTypeLabel_1 BIC_ServiceSelection_1 BIC_SongArtistLabel_1 BIC_ChannelReferenceLabel_1 ADF_ExtArtistLabel_1 ADF_ExtSongLabel_1 ADF_Text_1 ADF_ProgramStart_1 ADF_ProgramEnd_1 ADF_ProgramId_1 ADF_Other_1 ChNumChanged_0 ChNumChanged_1 0x48 0x47 0x46 Reg 0x45 Bit 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 Comment The radio is entered in maintenance mode The radio is entered in activation mode Universal Time Code I2C page ready to read by system controller The SDEC have received the CRB last block indication with new sequence number Received a new Service label for selection in location 0 Received a new Program Type label for selection in location 0 Received a new Service Selection message for selection in location 0 Received a new Song/Artist label for selection in location 0 Channel Reference Table changed for selection in location 0 Received a new Extended Artist label for selection in location 0 Received a new Extended Song label for selection in location 0 Received new Text message for selection in location 0 Received a new Program Start indication for selection in location 0 Received a new Program End indication for selection in location 0 Received a new Program ID indication for selection in location 0 Received a new Other message for selection in location 0 Received a new Service label for selection in location 1 Received a new Program type label for selection in location 1 Received a new Service Selection message for selection in location 1 Received a new Song/Artist label for selection in location 1 Channel Reference Table changed for selection in location 1 Received a new Extended Artist label for selection in location 1 Received a new Extended Song label for selection in location 1 Received new Text message for selection in location 1 Received a new Program Start indication for selection in location 1 Received a new Program End indication for selection in location 1 Received a new Program ID indication for selection in location 1 Received a new Other message for selection in location 1 The channel number is changed for SID extracted into location 0 The channel number is changed for SID extracted into location 1
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STA450A
HOST_ERRINTEH - HOST_ERRINTEL
7 4A 49 6 5 4 INTE[15:8] INTE[7:0] 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x4A - 0x49 : R/W : NA : NA
Description These registers are associated to error condition inside the STA450A. The STA450A contains a 16 bit interrupt register associated with 16 bit enable register. A bit set in this register will enable the generation of an external interrupt on the interrupt line. The interrupt associated with each bit is given in the register INT description.
HOST_ERRINTH - HOST_ERRINTL
7 4C 4B 6 5 4 INT[15:8] INT[7;0] 3 2 1 0
Address : 0x4B - 0x4C Type : R/W Software Reset : NA Hardware Reset : NA Description These registers are associated to error condition inside the STA450A. A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding bit in the INTE table has been set an external interrupt is generated. To clear the bit a fast command has to be issued (see command description).
Name Service Layer Lost Synchronization TSCC RSError Bitstream Communication Failure Service Layer incorrect status NoBacFromCdec Rollback PicIOError Audio Decoder Not Working NV Memory Unreadable ExtractionError_0 Reg Bit Comment 0x4B 0x01 Service Layer Lost synchronisation due to communication error with CDEC 0x02 TSCC have RS errors 0x04 The format of communication is not compatible with the bitstream input I/F. The DSP need to be restarted 0x08 Service Layer have reached an incorrect status. 0x10 The BAC wasn't received from the CDEC in the last frame 0x20 Error from decryption 0x40 Communication error with the CAP device 0x80 Error in the audio decoder 0x4C 0x01 Data corrupted in the NVM 0x02 Some error occurs during extraction of channel in location 0, to obtain detailed situation System Controller must raise a command. At the time of this command is raised the DSP clear the error buffer 0x04 Some error occurs during extraction of channel in location 1, to obtain detailed situation System Controller must raise a command. At the time of this command is raised the DSP clear the error buffer
ExtractionError_1
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STA450A
HOST_STARTUP
7 4D 6 5 4 3 2 1 0
Address : 0x4D Type : R/W Software Reset : NA Hardware Reset : NA Description Writing 0x01 in this register enables the STA450A sw to leave the wait mode and to start normal process. Using this register is also possible select special mode for silicon evaluation Before to set this register is mandatory to program the system PLL , the Audio Fractional PLL and to configure the PCM output format according to the application DAC. HOST_Pcmdiv
7 4E 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x4E : R/W : NA : NA
Description This register is red by STA450A before to leave the wait mode. The SCLK signal is derived from the clock PCMCLK.
HOST_pcmdiv = (0_FAC/64) -1 in 16 bit mode HOST_pcmdiv = (0_FAC/128) -1 in 18/20/24 bit mode If Pcm_div is set to 0, the SCLK frequency is equal to the PCMCLK frequency. HOST_Pcmcnf
7 4F 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x4F : R/W : NA : NA
Description This register is red by STA450A before to leave the wait mode. Pcm_prec Bit [1:0] 00: 16 bits mode. 01: 18 bits mode 10: 20 bits mode 11: 24 bits mode
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STA450A
Invert_sclk Bit 2 0: LRCLK and PCM_OUT sampled on the falling edge of the SCLK 1: LRCLK and PCM_OUT sampled on the raising edge of the SCLK Format Bit 3 0: the output is in I2S format. 1: the output is in SONY format. Invert_lrclk Bit 4 0: LRCLK = 0 (low) will select the left channel. 1: LRCLK = 1 (high) will select the left channel Pcm_dif Bit 5 0: data are in the last SCLK cycles of LRCLK (right aligned) 1: data are in the first SCLK cycles of LRCLK (left aligned) Pcm_ord Bit 6 0: the transmission is done LSB first. 1: the transmission is done MSB first. Pcm_iec_chansel Bit 7 0: no iec958 output. 1: iec958 output, data on I2S pin (PCSD) are no more valid. HOST_APLL48_LSB
7 50 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x50 : R/W : NA : NA
HOST_APLL48_MSB
7 51 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x51 : R/W : NA : NA
Description The HOST_APLL48_LSB and the HOST_APLL48_MSB are considered logically concatenated and contain the fractional values for the Audio Fractional PLL for the Fs = 48KHz family. The registers have to be programmed before the start_up of the DSP.
HOST_APLL48_XDIV
7 52 6 5 4 3 2 1 0
Address
: 0x52
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STA450A
Type Software Reset Hardware Reset : R/W : NA : NA
HOST_APLL48_MDIV
7 53 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x53 : R/W : NA : NA
HOST_APLL48_NDIV
7 54 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x54 : R/W : NA : NA
Description The HOST_APLL48_XDIV, HOST_APLL48_MDIV and HOST_APLL48_NDIV registers are used to configure the X, M and N divider of the Audio Fractional PLL for the Fs = 48KHz family. The registers have to be programmed before the start_up of the DSP.
.HOST_APLL441_LSB
7 50 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x55 : R/W : NA : NA
HOST_APLL441_MSB
7 51 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x56 : R/W : NA : NA
Description The HOST_APLL441_LSB and the HOST_APLL441_MSB are considered logically concatenated and
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STA450A
contain the fractional values for the Audio Fractional PLL for the Fs = 44.1KHz family. The registers have to be programmed before the start_up of the DSP. HOST_APLL441_XDIV
7 52 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x57 : R/W : NA : NA
HOST_APLL441_MDIV
7 53 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x58 : R/W : NA : NA
HOST_APLL441_NDIV
7 54 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x59 : R/W : NA : NA
Description The HOST_APLL441_XDIV, HOST_APLL441_MDIV and HOST_APLL441_NDIV registers are used to configure the X, M and N divider of the Audio Fractional PLL for the Fs = 44.1KHz family. The registers have to be programmed before the start_up of the DSP
ENABLE_IT432
7 5A 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x5A : R/W : NA : NA
Description Enabling of the Audio Fractional PLL control through the external 432ms interrupt on pin PLL_SYNC. 0: Disabled 1: Enabled
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STA450A
IT432_CONF
7 5B 6 5 4 3 2 1 0
Address : 0x5B Type : R/W Software Reset : NA Hardware Reset : NA Description Allows to configure if the 432ms interrupt is rising or falling edge sensitive. 0: sensitive to falling edge 1: sensitive to rising edge HOST_MAXDEV
7 5C 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x5C : R/W : NA : NA
Description Divider factor for deviation value window
HOST_Decoder BitRate
7 5D 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x5D : R/W : NA : NA
Description Audio decoder bit rate / 1K
HOST_BitstreamSynchro
7 5E 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x5E : R/W : NA : NA
Description 01: Not synchronised 10: Synchronised
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STA450A
HOST_DataPortBitRate
7 5F 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x5F : R/W : NA : NA
Description Data port bit rate / 1K (for bitrates 128Kbps 0xFF is reported) 10: Synchronised
HOST_EVENTINTE 4-5
7 66 67 6 5 4 INTE[15:8] INTE[7:0] 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x66 - 0x67 :R-W : NA : NA
Description These registers are associated to event condition inside the SDEC. The SDEC contains a 16 bits interrupt register associated with 16 bits enable register. A bit set in this register will enable the generation of an external interrupt on the interrupt line. The interrupt associated with each bit is given in the register INT description.
HOST_EVENTINT 4-5
7 68 69 6 5 4 INT[15:8] INT[7:0] 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x68 - 0x69 :R-W : NA : NA
Description These registers are associated to event condition inside the SDEC. A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding bit in the INTE table has been set an external interrupt is generated. To clear the bit a fast command has to be issued (see command description).
Name Fast extraction Loc0 Fast extraction Loc1 Reg 0x68 Bit 0x01 0x02 Comment Channel fast extraction for Loc0 successful Channel fast extraction for Loc1 successful
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Name CRW monitor list change Program Type (BIC 3) change Artist and Song change Service Label (BIC 5) change Program Label change BIC Extended Song label Loc0 BIC Text Label Loc0 BIC Extended Artist label Loc0 BIC Extended Song label Loc1 BIC Extended Artist label Loc1 BIC Text Label Loc1 RFU RFU RFU 0x69 Reg Bit 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 Comment Channel Reference Word list changed Program Type (BIC 3) changed Artist and Song changed Service Label (BIC 5) changed Program Label changed Extended Song label for Loc0 changed Text Label for Loc0 changed Extended Artist label for Loc0 changed Extended Song label for Loc1 changed Extended Artist label for Loc1 changed Text Label for Loc1 changed
HOST_ AudioDecResult
7 6B 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x6B : R/W : NA : NA
Description Upper nibble defines the decoder type: 0x10: AMBE 0x20: AAC Lower nibble defines the Audio decoder result. 0x00 data ok 0x01 error concealment (only for AAC) 0x02 synchronization lost, output muted
HOST_ MFC
7 6C 6 5 4 3 2 1 0
Address Type Software Reset Hardware Reset
: 0x6C : R/W : NA : NA
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Description Master Frame Counter LSB part (7 bits).
HOST_Page Ctrl
7 7F More 6 5 4 3 Byte Number-1 2 1 0
Address Type Software Reset Hardware Reset
: 0x7F : R/W : NA : NA
Description Bit 7 :more page to be download. This bit is used also as Hand Shake bit. The STA450A sets the bit as soon as the page is available and the System Controller clears the bit using the dedicated Fast command (see command description) as soon as the page has been read. In case the System Controller sends a new command and the MORE bit is set, the STA450A clears it automatically. Bit [6:0] :number - 1 of valid bytes in the current page
3.0 DSP COMMANDS QUICK REFERENCE References: Service Layer Specification XM Stack API Specification 3.1 Categories INIT 0x0X SELECT 0x1X INFO 0x2X MISC 0x3X FASTCMD 0x5X 3.2 COMMANDS
Command DSP_PWRUP_REQ DSP_PWRDWN_REQ FORCE_UPDATE CHANGE_DAC_CONF HARD_MUTE FADE_IN_OUT SOFT_MUTE DATAPORT_CH_FREQUENCY OpCode 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Category INIT INIT INIT INIT INIT INIT INIT INIT Description DSP Initialization command DSP Power Down command Force Update command Change DSP DAC configuration command Hard mute/play command Fade In/Fade Out command Soft mute/play command Change the divider for Data port
SERVICE_CHECK
0x10
SELECT
Check the status of a service using SID
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Command CHANNEL_CHECK CHANNEL_UP_DOWN PROGRAM_UP_DOWN SERVICE_EXTRACT EXTRACT_ERROR SERVICE_CANCEL SERVICE_ROUTING CHNCHECK_LIST_REQ EXTRACT_STATUS_REQ CHNSTATUS_LIST_REQ LABELMON_LIST_REQ OpCode 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0X18 0x19 0x1A 0x1B Category SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT SELECT After Fast extraction command the result is reported using this command Description Check the status of a service using channel number Channel search command Channel search trough Program type command Service extraction command Request service extraction error information Cancel a service currently extracted command Change the routing of an extracted command
SIB1_REQUEST SERV_LABEL_REQ (SIB 2) ARTSNG_LABEL_REQ (SIB 3) PTY_LABEL_REQ ALL_LABEL_REQ ADF_PROGRAM_ID_REQ ADF_PROGRAM_START_REQ ADF_PROGRAM_END_REQ ADF_EXTARTISTLBL_REQ ADF_EXTSONGLBL_REQ ADF_TEXT_REQ BIC_TEXT_REQ CHANNEL_REF_REQ ARTSNGCHG_LIST_REQ PROGTYPE_LIST_REQ
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2C 0x2D 0x2E 0x2F
INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO
SIB 1 request SIB 2 request SIB 3 request Program Type label request All label request Program ID request Program Start request Program End request Extended Artist label request Extended Song label request Text message request BIC Text request Channel Table request
HWID_READ_REQ UTC_REQ CLEAR_DATA_REQ PROGLABEL_LIST_REQ BIC_LABEL_REQ
0x31 0x32 0x34 0x36 0x37
MISC MISC MISC MISC MISC
HW ID request Universal Time Code and Master Frame Counter request
Ram
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Command DISPLAY_MASK_REQ SDEC_VER_REQ OpCode 0x4C 0x4D Category SERVICE SERVICE Description This command must be issued before power up This command must be issued before power up The system controller can selected the version of the SDEC
FAST_CLEAR_EVENT FAST_DISABLE_REQ FAST_ENABLE _REQ FAST_EXTRACT_REQ
0x50 0x51 0x52 0x53
FASTR FASTR FASTR FASTR
Clear events and error bit according to applied mask Clear events and error interrupt enable bit according to applied mask Set events and errors interrupt enable bits according to applied mask Service extract in fast mode
3.3 DSP COMMAND DESCRIPTION The commands are composed by two parts: the REQ one (request) and the CFM one (confirmation). The REQ has to be written in the Command registers (0x6D - 0x7E); the CFM has to be read in the Data Page registers (0x80 - 0xFF). After a REQ has been issued the STA450A replies with a CFM within 5 MFP (5 x 432ms).
3.3.1
DSP_PWRUP_REQ
FIELD DSP_PWRUP_REQ serv_label_size gen_label_size 0x00 8, 12, 16 8, 12, 16 VALUE DESCRIPTION DSP Initialization Request header Display size for the service label. Display size for the song label, artist label, and program label. VALUE 0x80 0x00 - NO ERROR 0x01 - CAP_IO_ERROR 0x02 - INVALID_NVM_IMAGE 0x04 - ACT_PRESENT 0x00 - ACT_ABSENT DESCRIPTION DSP Initialization Confirm header DSP power up error status
BYTE 0 1 2
BYTE 0 1
FIELD DSP_ PWRUP _CFM error_code
2
init_complete_status
Activation Status If both encryption keys are stored in memory, then DSP reports ACT_PRESENT. If no encryption keys are stored in memory, then DSP reports ACT_ABSENT. Last saved Entered Authorization Rating (EAR) DSP software version DSP release date. The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
3 4 5-8
last_ear dsp_sw_version dsp_sw_date
0-3 0x00 - 0xFF Byte 5: month in BCD. Byte 6: day in BCD. Bytes 7,8: Year in BCD.
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9 - 12 last_crw0 Last Channel Reference Word (CRW) for location zero Reference: Service Layer Specification Last Service Component type for location zero Reference: Service Layer Specification Last Channel Reference Word (CRW) for location one Reference: Service Layer Specification Last Service Component type for location one. Reference: Service Layer Specification Hardware Identification
13
last_sc_type0
14 - 17
last_crw1
18
last_sc_type1
19 - 26
Hwid
3.3.2
BYTE 0 BYTE 0 1-2
DSP_PWRDWN_REQ
FIELD DSP_PWRDWN_REQ FIELD DSP_PWRDWN_CFM error_code 0x81 0x01 - CAP IO Error 0x02 - Invalid image 0x01 VALUE VALUE DESCRIPTION DSP Power Down Request header DESCRIPTION DSP Power Down Confirm header Power down error code.
3.3.3
FORCE_UPDATE
FIELD FORCE_UPDATE_REQ FIELD FORCE_UPDATE_CFM 0x82 0x02 VALUE VALUE DESCRIPTION Force Update Request header DESCRIPTION Force Update Request header
BYTE 0 BYTE 0
3.3.4
CHANGE_DAC_CONF
FIELD CHANGE_DAC_CONF_REQ Pcm_divider Pcm_configuration FIELD CHANGE_DAC_CONF_CFM 0x83 VALUE DESCRIPTION DSP DAC configuration confirmation 0x03 VALUE DESCRIPTION DSP DAC configuration Request header
BYTE 0 1 2 BYTE 0
3.3.5
HARD_MUTE
FIELD HARD_MUTE_REQ Pcm_playmue 0x04 1 - play 2 - hard mute VALUE DESCRIPTION DSP hard mute Request header
BYTE 0 1
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BYTE 0 FIELD HARD_MUTE_CFM 0x84 VALUE DESCRIPTION DSP hard mute confirmation
3.3.6
FADE_IN_OUT
FIELD FADE_IN_OUT _REQ nr_fadeout_frames nr_fadein_frames nr_valide_frames cmftNoiseLimit 0x05 0x03 - Default 0x05 - Default 0x05 - Default 0x00 - Min 0x01 - Default 0x64 (100) - Max 0x06 - Default 0x05 - Default VALUE DESCRIPTION DSP Fade In/Out Request header Number of fadeout frames until mute state is reached for frequencies less than 32kbps Number of fadein frames until regular state is reached for frequencies less than 32kbps Number of valid frames before fadein starts for frequencies less than 32kbps This parameter give the maximum level for `comfort noise'. This must be the percentage value respect to the maximum (for frequencies less than 32kbps) Number of fadeout frames until mute state is reached for frequencies greater than 32kbps Number of fadein frames until regular state is reached for frequencies greater than 32kbps Number of valid frames before fadein starts for frequencies greater than 32kbps This parameter give the maximum level for `comfort noise'. This must be the percentage value respect to the maximum (for frequencies greater than 32kbps) DESCRIPTION DSP Fade In/Out confirmation 0x01 = success 0xFF = command not executed
BYTE 0 1 2 3 4
5 6
nr_fadeout_frames nr_fadein_frames
7 8
nr_valide_frames cmftNoiseLimit
0x05 - Default 0x00 - Min 0x01 - Default 0x64 (100) - Max
BYTE 0 1
FIELD FADE_IN_OUT _CFM Command status 0x85
VALUE
3.3.7
SOFT_MUTE
FIELD SOFT_MUTE_REQ Soft_playmute 0x06 0 - play 1 - soft mute VALUE 0x86 DESCRIPTION DSP soft mute confirmation VALUE DESCRIPTION DSP soft mute Request header
BYTE 0 1
BYTE 0
FIELD SOFT_MUTE_CFM
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3.3.8 DATAPORT_CH_FREQUENCY
FIELD DP_CF_REQ Data port frequency divider 0x07 Max. 0x05 - 12 Mhz Default 0x1E - 2 Mhz Min. 0x3C - 1Mhz VALUE DESCRIPTION Data port change frequency Request header System clock divider. E.g. Divider = 0x1E (30) DpClk = (SysClk / 12); DpClk = (60 Mhz / 12) = 2 Mhz DESCRIPTION Data port change frequency confirmation
BYTE 0 1
BYTE 0
FIELD DP_CF_CFM 0x87
VALUE
3.3.9
SERVICE_CHECK
FIELD SERVICE_CHECK_REQ Sid extract_type 0x10 1-255 0x00 - Audio 0x01 - Data VALUE DESCRIPTION Service Check Request header Service identifier Service type to extract. MMI can extract the audio or data service component.
BYTE 0 1 2
BYTE 0 1
FIELD SERVICE_CHECK_CFM service_check_status 0x90
VALUE
DESCRIPTION Service Check Confirm header The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
bit 7 - Service Present 0x80 - SID_PRESENT 0x00 - SID_ABSENT bit 6 - PC Format 0x40 - PC_STANDARD 0x00 - PC_NONSTANDARD bit 5 - Service On-Air 0x20 - SERVICE_ONAIR 0x00 - SERVICE_OFFAIR bit 4 - Service Type 0x10 - TYPE_PRESENT 0x00 - TYPE_ABSENT bit 3 - Service Free 0x08 - SERVICE_FREE 0x00 - SERVICE_NOTFREE bit 2 - Activation 0x04 - ACT_PRESENT 0x00 - ACT_ABSENT bit 1 - Authorization 0x02 - AUTH_PRESENT 0x00 - AUTH_ABSENT b0 - Reserved 1 - 255
2 3,4,5,6
channel_number crw
channel number for the service Channel Reference Word Reference: Service Layer Specification.
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3.3.10 CHANNEL_CHECK
BYTE 0 1 2 FIELD CHANNEL_CHECK_REQ channel_number extract_type 0x11 1-255 0x00 - Audio 0x01 - Data VALUE DESCRIPTION Channel Check Request header Channel number Service component type to extract. MMI can extract the audio or data service component. DESCRIPTION Channel Check Confirm header The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
BYTE 0 1
FIELD CHANNEL_CHECK_CFM service_check_status 0x91
VALUE
bit 7 - Service Present 0x80 - SID_PRESENT 0x00 - SID_ABSENT bit 6 - PC Format 0x40 - PC_STANDARD 0x00 - PC_NONSTANDARD bit 5 - Service On-Air 0x20 - SERVICE_ONAIR 0x00 - SERVICE_OFFAIR bit 4 - Service Type 0x10 - TYPE_PRESENT 0x00 - TYPE_ABSENT bit 3 - Service Free 0x08 - SERVICE_FREE 0x00 - SERVICE_NOTFREE bit 2 - Activation 0x04 - ACT_PRESENT 0x00 - ACT_ABSENT bit 1 - Authorization 0x02 - AUTH_PRESENT 0x00 - AUTH_ABSENT b0 - Reserved
2,3,4,5 6
crw sib1_status 0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT
Channel Reference Word Reference: Service Layer Specification If service information block 1 was not received, then DSP returns SIB1_ABSENT. If service information block 1 was received, then DSP returns SIB1_PRESENT Service Information Block 1 Reference: Service Layer Specification.
7 to 14
service_block1
3.3.11 CHANNEL_UP_DOWN
BYTE 0 1 2 3 4 FIELD CHANNEL_UPDWN_REQ Direction channel_start_number channel_end_number extract_type 0x12 0x00 - UP 0x01 - DOWN 1-255 1-255 0x00 - Audio 0x01 - Data VALUE DESCRIPTION Channel Up/Down Request header Direction to search Channel start number Channel end number Service type to extract. MMI can extract the audio or data service component.
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BYTE 0 1 FIELD CHANNEL_UPDWN_CFM search_status VALUE 0x92 bit 7 - Search Outcome 0x80 - SEARCH_SUCCESSFUL 0x00 - SEARCH_FAIL bit 6 - Extract Type 0x40 - TYPE_PRESENT 0x00 - TYPE_ABSENT bit 5 - Reserved bit 4 - Reserved bit 3 - Reserved bit 2 - Reserved bit 1 - Reserved bit 0 - Reserved 1 - 255 DESCRIPTION Channel Up/Down Confirm header The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
2 3,4,5,6 7
channel_number crw sib1_status
0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT
8 to 15
service_block1
channel number Channel Reference Word Reference: Service Layer Specification If service information block 1 was not received, then DSP returns SIB1_ABSENT. If service information block 1 was received, then DSP returns SIB1_PRESENT. Service Information Block 1 Reference: Service Layer Specification
3.3.12 PROGRAM_UP_DOWN
BYTE 0 1 2 3 4 5 FIELD PROGRAM_UPDWN_REQ Direction channel_start_number channel_end_number program_type extract_type 0x13 0x00 - UP 0x01 - DOWN 1-255 1-255 1-31 0x00 - Audio 0x01 - Data VALUE 0x93 bit 7 - Search Outcome 0x80 - SEARCH_SUCCESSFUL 0x00 - SEARCH_FAIL bit 6 - Extract Type 0x40 - TYPE_PRESENT 0x00 - TYPE_ABSENT bit 5 - Reserved 0x20 - PROGRAM_PRESENT 0x00 - PROGRAM_ABSENT bit 4 - Reserved bit 3 - Reserved bit 2 - Reserved bit 1 - Reserved bit 0 - Reserved 1 - 255 VALUE DESCRIPTION Program Up/Down Request header Direction to search Channel start number Channel end number Program type Service type to extract. MMI can extract the audio or data service component. DESCRIPTION Program Up/Down Confirm header The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
BYTE 0 1
FIELD PROGRAM_UPDWN_CFM search_status
2
channel_number
channel number for the service
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3,4,5,6 7 crw sib1_status 0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT Channel Reference Word Reference: Service Layer Specification If service information block 1 was not received, then DSP returns SIB1_ABSENT. If service information block 1 was received, then DSP returns SIB1_PRESENT. Service Information Block 1 Reference: Service Layer Specification
8 to 15
service_block1
3.3.13 SERVICE_EXTRACT
BYTE 0 1 FIELD SERVICE_EXTRACT_REQ location 0x14 0x00 - location 0 0x01 - location 1 0x0001 to 0xFFFF VALUE DESCRIPTION Service Extract Request header Since DSP can extract two services simultaneously, XM stack assigns an extraction location. Number of master frame that the DSP waits for the primary PCID or secondary PCID. Service Identifier Service Component Type Reference: Service Layer Specification; page 21 Primary Payload Channel Identification Reference: Transport Layer Specification Secondary Payload Channel Identification Reference: Transport Layer Specification Routing information A data service component can only be routed to the data port (DAT_PORT). An audio service component be routed to audio port (AUD_PORT), data port (DAT_PORT) or both the audio and data port (BOTH_PORT). DESCRIPTION Service Extract Confirm header Location assigned to the service. If the command was refused the location is set to 0xFF. This can happen if the extraction of a component with routing for audio port is commanded and a component with routing audio port is already extracted in the other location or if an inexistent location is passed to the DSP
2-3
pc_detect_time
4 5
sid sc_type
1 - 255 0x03 - Audio AMBE 0x05 - Audio AAC+ 0x0A - Trans. Data 5 - 255 5 - 255
6 7
primary_pcid Secondary_pcid
8
Routing
0x00 0x01 0x02 0x03
- No routing - AUD_PORT - DAT_PORT - BOTH_PORT
BYTE 0 1
FIELD SERVICE_EXTRACT_CFM Location 0x94
VALUE
0x00 - location 0 0x01 - location 1 0xFF - command refused
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2 extract_error_status bit 7 - PC Detect 0x80 - PCID_UNDETECTED 0x00 - PCID_DETECTED bit 6 - Service Detect 0x40 - SID_UNDETECTED 0x00 - SID_DETECTED bit 5 - SC Type Detect 0x20 - SCT_UNDETECTED 0x00 - SCT_DETECTED bit 4 - Authorisation 0x10 - AUTH_MISSING 0x00 - AUTH_OK bit 3 - EAR Low 0x08 - EAR_LOW 0x00 - EAR_OK bit 2 - RAT Block 0x04 - RAT_BLOCK 0x00 - RAT_OK bit 1 - RAT Low 0x02 - RAT_LOW 0x00 - RAT_OK b0 - TOD Rollback 0x01 - TOD_ROLLBACK 0x00 - TOD_OK The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
3.3.14 EXTRACT_ERROR
BYTE 0 1 Location FIELD EXTRACT_ERROR_REQ 0x15 0x00 - location 0 0x01 - location 1 0x02 - generic error (TEST only) FIELD EXTRACT_ERROR_CFM extract_error_status 0x95 bit 7 - PC Detect 0x80 - PCID_UNDETECTED 0x00 - PCID_DETECTED bit 6 - Service Detect 0x40 - SID_UNDETECTED 0x00 - SID_DETECTED bit 5 - SC Type Detect 0x20 - SCT_UNDETECTED 0x00 - SCT_DETECTED bit 4 - Authorisation 0x10 - AUTH_MISSING 0x00 - AUTH_OK bit 3 - EAR Low 0x08 - EAR_LOW 0x00 - EAR_OK bit 2 - RAT Block 0x04 - RAT_BLOCK 0x00 - RAT_OK bit 1 - RAT Low 0x02 - RAT_LOW 0x00 - RAT_OK b0 - TOD Rollback 0x01 - TOD_ROLLBACK 0x00 - TOD_OK VALUE VALUE DESCRIPTION Extract Error Request header DSP reports errors for the selected location or errors related to the data analysis and extraction (test only).
BYTE 0 1
DESCRIPTION Extract Error Confirm header The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0. If the command is refused 0xFF is returned
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3.3.15 SERVICE_CANCEL
BYTE 0 1 FIELD SERVICE_CANCEL_REQ location 0x16 0x00 - location 0 0x01 - location 1 VALUE DESCRIPTION Service Cancel Request header Since DSP can extract two services simultaneously, XM stack specifies which location to cancel.
BYTE 0 1
FIELD SERVICE_CANCEL_CFM location 0x96
VALUE
DESCRIPTION Service Cancel Confirm header DSP reports the extraction location that was cancelled. If the command is refused 0xFF is returned
0x00 - location 0 0x01 - location 1
3.3.16 SERVICE_ROUTING
BYTE 0 1 FIELD SERVICE_ROUTING_REQ location 0x17 0x00 - location 0 0x01 - location 1 0x00 0x01 0x02 0x03 FIELD SERVICE_ROUTING_CFM location 0x97 0x00 - location 0 0x01 - location 1 0x00 0x01 0x02 0x03 - No routing - AUDIO_PORT - DATA_PORT - BOTH_PORT - No routing - AUDIO_PORT - DATA_PORT - BOTH_PORT VALUE VALUE DESCRIPTION Service Routing Request header Since DSP can extract two services simultaneously, XM stack specifies which location to change the routing Routing information
2
routing
BYTE 0 1
DESCRIPTION Service Routing Confirm header Location that changed routing. If the command is refused 0xFF is returned New routing configuration. If the command is refused the old routing status is returned
2
routing
3.3.17 CHCHECK_LIST_REQ
BYTE 0 1 2 FIELD CHNCHECK_LIST_REQ extract_type prog_type_flag 0x18 0x00 - Audio 0x01 - Data 0x00 - FALSE 0x01 - TRUE VALUE DESCRIPTION Channel Check List Request Header MMI can extract the audio or data service component. If the MMI is requesting only the channels belonging to a program type, then the prog_type_flag is set to TRUE. If the MMI is requesting all channels, then the prog_type_flag is set to FALSE. If the prog_type_flag is set to TRUE, then the SDEC reports the service labels that only belongs to this program type.
3
program_type
1 - 31
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BYTE 0 1 2 FIELD CHNCHECK_LIST_CFM Command_status channel_bit_mask00 0x98 0x01 - succesful 0xFF - failure bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - ...... ...... ...... bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - channel 255 channel 254 channel 253 channel 252 channel 251 channel 250 channel 249 channel 248 channel 007 channel 006 channel 005 channel 004 channel 003 channel 002 channel 001 channel 000 channel 015 channel 014 channel 013 channel 012 channel 011 channel 010 channel 009 channel 008 channel 023 channel 022 channel 021 channel 020 channel 019 channel 018 channel 017 channel 016 Channel mask 0 - channel status indication bits for channels 0 to channel 7. VALUE DESCRIPTION Channel Check List Confirm Header
3
channel_bit_mask01
Channel mask 1 - channel status indication bits for channels 8 to channel 15.
4
channel_bit_mask02
Channel mask 3 - channel status indication bits for channels 16 to channel 23.
...... ...... ...... 33
...... ...... ...... channel_bit_mask31
....... ....... ....... Channel mask 32 - channel status indication bits for channels 248 to channel 255.
3.3.18 EXTRACT_STATUS_REQ
BYTE 0 1 FIELD EXTRACT_STATUS_REQ location 0x19 0x00 - location 0 0x01 - location 1 VALUE DESCRIPTION Extract Status Request header Since SDEC can extract two services simultaneously, XM stack specifies which location to get the extraction errors
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BYTE 0 1 FIELD EXTRACT_STATUS_CFM location 0x99 0x00 - location 0 0x01 - location 1 1-255 1-255 0x00 - Not initiated 0x01 - In progress 0x02 - Ok 0x03 - Incorrect parameter in command. bit 7 - PC Detect 0x80 - PCID_UNDETECTED 0x00 - PCID_DETECTED bit 6 - Service Detect 0x40 - SID_UNDETECTED 0x00 - SID_DETECTED bit 5 - SC Type Detect 0x20 - SCT_UNDETECTED 0x00 - SCT_DETECTED bit 4 - Authorization 0x10 - AUTH_MISSING 0x00 - AUTH_OK bit 3 - Reserved bit 2 - RAT Block 0x04 - RAT_BLOCKED 0x00 - RAT_UNBLOCKED bit 1 - RAT Low 0x02 - RAT_LOW 0x00 - RAT_OK b0 - TOD Rollback 0x01 - TOD_ROLLBACK 0x00 - TOD_OK Byte 6: LSB byte Byte 7: Middle byte Byte 8: MSB byte The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0 VALUE DESCRIPTION Extract Status Confirm header Since SDEC can extract two services simultaneously, system controller assigns an extraction location. Extracted channel number SID of location 0 extraction.
2 3 4
Channel number SID Extraction status
5
extract_error_status
6-8
Counter
If status=0, counter = 0 For all other status, counter is #x432ms for actual time, counter will be running free until a channel is selected or initialized on the next fast extract command
3.3.19 CHANNEL STATUS_LIST_REQ
BYTE 0 1 2 3 FIELD CHNSTATUS_LIST_REQ start_channel_number channel_number extract_type 0x1A 1 - 255 1 to 32 max 0x00- Audio 0x01 - Data VALUE DESCRIPTION Channel Status List Request Header The channel number where the SDEC starts the status check. number of selectable channels will be returned MMI can extract the audio or data service component.
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4 prog_type_flag 0x00 - FALSE 0x01 - TRUE If the MMI is requesting only the service labels belonging to a program type, then the prog_type_flag is set to TRUE. If the MMI is requesting all service labels, then the progtype_filter_flag is set to FALSE. If the prog_type_flag is set to TRUE, then the SDEC reports the service labels that only belongs to this program type. if the crw_report-flag is set to TRUE, then the SDEC reports the CRW for each selectable channel requested. if the sib1_report_flag is set to TRUE, then the SDEC reports the program types for each selectable channel requested. if the sib2_report_flag is set to TRUE, then the SDEC reports SIB2t (service selectable) for each selectable channel requested. if the sib3_report_flag is set to TRUE, then the SDEC reports SIB3( artist name and song title) for each selectable channel requested.
5
program_type
1 - 31
6
crw_report _flag
0x00 - FALSE 0x01 - TRUE 0x00 - FALSE 0x01 - TRUE
7
sib1_report_flag
8
sib2_report_flag
0x00 - FALSE 0x01 - TRUE
9
sib3_report_flag
0x00 - FALSE 0x01 - TRUE
BYTE 0 1-2
FIELD CHNSTATUS_LIST_CFM size 0x9A
VALUE
DESCRIPTION Channel Status List Confirm Header Size in byte of the Channel Status List Confirm response. The size excluding byte 0, 1, 2 MSB in byte 1. LSB in byte 2. The channel number of the first available service label. The bits are ordered from left to right. The MSB is on the left and the LSB is on the right. b7, b6, b5, b4, b3, b2, b1, b0
0x0000 to 0x07A0 (bytes)
3 4
channel_number service_check_status
1 - 255 bit 7 - Reserved bit 6 - PC Format 0x40 - PC_STANDARD 0x00 - PC_NONSTANDARD bit 5 - Service On-Air 0x20 - SERVICE_ONAIR 0x00 - SERVICE_OFFAIR bit 4 - Reserved bit 3 - Service Free 0x08 - SERVICE_FREE 0x00 - SERVICE_NOTFREE bit 2 - Activation 0x04 - ACT_PRESENT 0x00 - ACT_ABSENT bit 1 - Authorization 0x02 - AUTH_PRESENT 0x00 - AUTH_ABSENT b0 - Reserved
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5-8 crw Channel Reference Word Reference: Service Layer Specification Revison 1.2, page 38 and 56. 0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT 1 - 31 The channel's first program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. 11 program_type1 1 - 31 The channel's second program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. 12 program_type2 1 - 31 The channel's third program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. 13 program_type3 1 - 31 The channel's fourth program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type 14 15 to 30 sib2_status service_label 0x00 - SIB2_ABSENT 0x01 - SIB2_PRESENT ISO-8859-1 character set SIB2 status The service label (SIB2). Note If sib2 is ABSENT, SDEC inserts 0x00 for all 16 characters. 31 32 to 47 sib3_status artist_name 0x00 - SIB3_ABSENT 0x01 - SIB3_PRESENT ISO-8859-1 character set SIB3 status artist_name Note If sib3 is ABSENT, SDEC inserts 0x00 for all 16 characters. 48 to 63 song_title ISO-8859-1 character set song title Note If sib3 is ABSENT, SDEC inserts 0x00 for all 16 characters. ...... ...... ...... size - 61 size - 60 ...... ...... ...... channel_number service_check_status ...... ...... ...... 1- 255 same as above ...... ...... ...... The channel number of the last available service label same as above Channel Reference Word Reference: Service Layer Specification Revison 1.2, page 38 and 56. 0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT sib1 status
9 10
sib1_status program_type0
size - 59 crw to size -54 size - 55 sib1_status
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size - 54 program_type0 1 - 31 The channel's first program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. size - 53 program_type1 1 - 31 The channel's second program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. size - 52 program_type2 1 - 31 The channel's third program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. size - 51 program_type3 1 - 31 The channel's fourth program type. Note if SIB1 is absent, SDEC inserts 0x00 for program type. size - 50 size - 49 to size - 32 size - 33 to size - 31 size - 32 to size - 15 size - 16 to size - 1 sib2_satus service_label 0x00 - SIB2_ABSENT 0x01 - SIB2_PRESENT ISO-8859-1 character set. SIB2 status The service label (SIB2) Note If sib2 is ABSENT, SDEC inserts 0x00 for all 16 characters SIB3 status
sib3_satus
0x00 - SIB3_ABSENT 0x01 - SIB3_PRESENT ISO-8859-1 character set.
artist_name
artist name Note If sib3 is ABSENT, SDEC inserts 0x00 for all 16 characters song title. Note If sib3 is ABSENT, SDEC inserts 0x00 for all 16 characters
song_title
ISO-8859-1 character set.
3.3.20 LABELMON_LIST_REQ
BYTE 0 1 FIELD LABELMON_LIST_REQ monitor_request 0x1B 0x00 - monitor label changes for all channels. 0x01 (NEW) 0x03 (ADD) - monitor label changes for channels listed below (from byte 23 to byte 16). 0x01 means the start of a new list. 0x03 means the updating of a list. In this way giving this command more than 1 time you can choose every channel number to test 0x02 (NEW) - 0x04 (ADD) monitor label changes for channels that belongs to program types listed below (from byte 2 to byte 16) VALUE DESCRIPTION Label Monitor List Request Header The channel monitor type. Note if monitor request set to 0x00 (all channels), this command is only two byte.
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2 channel_program0 For channel number values is: 1 - 255 For program type values is : 1 - 31 ..... ..... For channel number values is: 1 - 255 For program type values is: 1 - 31 VALUE 0x9B 0x00 - monitor label changes for all channels. 0x01/0x03 - monitor label changes for channels listed below (from byte 23 to byte16) 0x02/0x04 - monitor label changes for channels that belongs to program types listed below (from byte 2 to byte 16) If monitor request is set to 0x01, this byte is a channel number (1-255). If the monitor request is set to 0x02, this byte is a program type (1-31). ..... ..... If monitor request is set to 0x01, this byte is a channel number (1-255). If the monitor request is set to 0x02, this byte is a program type (1-31). DESCRIPTION Label Monitor List Confirm Header The channel monitor type. Note if monitor request set to 0x00 (all channels), this command is only two byte.
..... ..... 17
..... ..... channel_program15
BYTE 0 1
FIELD LABELMON_LIST_CFM monitor_request
3.3.21 SIB1_REQUEST
BYTE 0 1 FIELD SERVICE_SELECTION_REQ channel_number 0x20 1-255 VALUE DESCRIPTION Service Selection Request header Channel number for which DSP returns the Service Selection contained in Service Information Block 1. VALUE 0xA0 0x00 - SIB1_ABSENT 0x01 - SIB1_PRESENT DESCRIPTION Service Selection Confirm header If SIB1 was not received, then DSP returns SIB1_ABSENT. If SIB2 was received, then DSP returns SIB1_PRESENT. Service identifier Service Information Block 1 (SIB1). The service selection is contained in SIB1. Reference: Service Layer Specification.
BYTE 0 1
FIELD SERVICE_SELECTION_CFM sib1_status
2 3 - 10
sid service_block1
1-255
3.3.22 SERV_LABEL_REQ (SIB 2)
BYTE 0 1 FIELD SERVICE_LABEL_REQ channel_number 0x21 1-255 VALUE DESCRIPTION Service Label Request header Channel number for which DSP returns the Service Label.
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BYTE 0 1 FIELD SERVICE_LABEL_CFM sib2_status 0xA1 0x00 - SIB2_ABSENT 0x01 - SIB2_PRESENT VALUE DESCRIPTION Service Label Confirm header If SIB2 was not received, then DSP returns SIB2_ABSENT. If SIB2 was received, then DSP returns SIB2_PRESENT. Service identifier Service Information Block 2 (SIB2). The artist and song label are contained in SIB2. Reference: Service Layer Specification
2 3 - 18
sid service_block2
1-255
3.3.23 ARTSNG_LABEL_REQ (SIB 3)
BYTE 0 1 FIELD ARTSNG_LABEL_REQ channel_number 0x22 1-255 VALUE DESCRIPTION Artist/Song Label Request header Channel number for which DSP returns the Artist/Song Label. VALUE 0xA2 0x00 - SIB3_ABSENT 0x01 - SIB3_PRESENT DESCRIPTION Artist/Song Label Confirm header If SIB3 was not received, then DSP returns SIB3_ABSENT. If SIB3 was received, then DSP returns SIB3_PRESENT Service identifier Service Information Block 3 (SIB3). The artist and song label are contained in SIB3. Reference: Service Layer Specification.
BYTE 0 1
FIELD ARTSNG_LABEL_CFM sib3_status
2 3 - 39
sid service_block3
1-255
3.3.24 PTY_LABEL_REQ
BYTE 0 1 FIELD PROGRAM_LABEL_REQ program_type 0x23 1 - 31 VALUE DESCRIPTION Program Label Request header Program type. The program type is used as an index into the program label table to obtain the program label. VALUE 0xA3 0x00 - PROGLABEL_ABSENT 0x01 - PROGLABEL_PRESENT DESCRIPTION Program Label Confirm header If the program label was not received, then DSP returns PROGLABEL_ABSENT. If the program label was received, then DSP returns PROGLABEL_PRESENT.
BYTE 0 1
FIELD PROGRAM_LABEL_CFM program_label_status
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2 - 17 program_label Program label. Reference: Service Layer Specification
3.3.25 ALL_LABEL_REQ
BYTE 0 1 2 FIELD ALL_LABEL_REQ channel_number program_type 0x24 1-255 1 - 31 VALUE DESCRIPTION All Label Request header Channel number for which DSP returns the labels. Program type The program type is used as an index into the program label table to obtain the program label. VALUE 0xA4 0x00 - SIB2_ABSENT 0x01 - SIB2_PRESENT DESCRIPTION All Label Confirm header If the service information block 2 was not received, then DSP returns SIB2_ABSENT. If the service information block 2 was received, then DSP returns SIB2_PRESENT. Service Information Block 2 (SIB2). The service label is contained in SIB2. Reference: Service Layer Specification 0x00 - SIB3_ABSENT 0x01 - SIB3_PRESENT If the service information block 3 was not received, then DSP returns SIB3_ABSENT. If the service information block 3 was received, then DSP returns SIB3_PRESENT. Service Information Block 3 (SIB3). The artist label and song label is contained in SIB3. Reference: Service Layer Specification 0x00 - PROGLABEL_ABSENT 0x01 - PROGLABEL_PRESENT If the program label was not received, then DSP returns PROGLABEL_ABSENT. If the program label was received, then DSP returns PROGLABEL_PRESENT. Program label. Reference: Service Layer Specification.
BYTE 0 1 sib2_status
FIELD ALL_LABEL_CFM
2 - 17
service_block2
18
sib3_status
19 - 55
service_block3
56
program_label_status
57 - 72
program_label
3.3.26 ADF_PROGRAM_ID_REQ
BYTE 0 1 FIELD PROGRAM_ID_REQ sid 0x25 1-255 VALUE DESCRIPTION Program Identification Request header Service identifier for which DSP returns the program Identification. VALUE 0xA5 DESCRIPTION Program Identification Confirm header
BYTE 0
FIELD PROGRAM_ID_CFM
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1 adf_status 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT If the program Identification ADF was not received, then DSP returns ADF_ABSENT. If the program Identification ADF was received, then DSP returns ADF_PRESENT. Program Identification ADF. Reference: Service Layer Specification.
2-6
adf_progid
3.3.27 ADF_PROGRAM_START_REQ
BYTE 0 1 FIELD PROGRAM_START_REQ sid 0x26 1-255 VALUE DESCRIPTION Program Start Request header Service identifier for which DSP returns the program start time. VALUE 0xA6 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT DESCRIPTION Program Start Confirm header If the program start ADF was not received, then DSP returns ADF_ABSENT. If the program start ADF was received, then DSP returns ADF_PRESENT. Program Start ADF. Reference: Service Layer Specification.
BYTE 0 1
FIELD PROGRAM_START_CFM adf_status
2-3
adf_progst
3.3.28 ADF_PROGRAM_END_REQ
BYTE 0 1 FIELD PROGRAM_END_REQ sid 0x27 1-255 VALUE DESCRIPTION Program End Request header Service identifier for which DSP returns the program and time. VALUE 0xA7 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT DESCRIPTION Program End Confirm header If the program end ADF was not received, then DSP returns ADF_ABSENT. If the program end ADF was received, then DSP returns ADF_PRESENT. Program End ADF. Reference: Service Layer Specification.
BYTE 0 1
FIELD PROGRAM_END_CFM adf_status
2-3
adf_progend
3.3.29 ADF_EXTARTISTLBL_REQ
BYTE 0 1 FIELD EXTART_LABEL_REQ sid 0x28 1-255 VALUE DESCRIPTION Extended Artist Label Request header Service identifier for which DSP returns the extended artist label. VALUE DESCRIPTION
BYTE
FIELD
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0 1 EXTART_LABEL_CFM adf_status 0xA8 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT Extended Artist Label Confirm header If extended artist ADF was not received, then DSP returns ADF_ABSENT. If extended artist ADF was received, then DSP returns ADF_PRESENT. Extended Artist ADF. Reference: Service Layer Specification.
2 - 34
adf_extart
3.3.30 ADF_EXTSONGLBL_REQ
BYTE 0 1 FIELD EXTSNG_LABEL_REQ sid 0x29 1-255 VALUE DESCRIPTION Extended Song Label Request header Service identifier for which DSP returns the extended song label. VALUE 0xA9 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT DESCRIPTION Extended Song Label Confirm header If extended song ADF was not received, then DSP returns ADF_ABSENT. If extended song ADF was received, then DSP returns ADF_PRESENT. Extended Song Label ADF. Reference: Service Layer Specification.
BYTE 0 1
FIELD EXTSNG_LABEL_CFM adf_status
2 - 34
adf_extsng
3.3.31 ADF_TEXT_REQ
BYTE 0 1 FIELD CHANNEL_TEXT_REQ sid 0x2A 1-255 VALUE DESCRIPTION Channel Text Request header Service identifier for which DSP returns the text. VALUE 0xAA 0x00 - ADF_ABSENT 0x01 - ADF_PRESENT DESCRIPTION Channel Text Confirm header If text ADF was not received, then DSP returns ADF_ABSENT. If text ADF was received, then DSP returns ADF_PRESENT. Text ADF. Reference: Service Layer Specification.
BYTE 0 1
FIELD CHANNEL_TEXT_CFM adf_status
2 - 260
adf_text
3.3.32 BIC_TEXT_REQ
BYTE 0 1 FIELD BIC_TEXT_REQ sid 0x2C 1-255 VALUE DESCRIPTION BIC Text Request header Service identifier for which DSP returns the text.
BYTE
FIELD
VALUE
DESCRIPTION
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0 1 BIC_TEXT_CFM BIC_text_status 0xAC 0x00 -ABSENT 0x01 - PRESENT 1-255 see specification BIC text Confirm header If BIC text was not received, then DSP returns ABSENT. If BIC text was received, then DSP returns PRESENT. SID Scrolling and narrowcast information. Reference: Service Layer Specification; revision 1.4; section 8.11. Length of the text message. BIC Text Reference: Service Layer Specification; revision 1.4; section 8.11.
2 3
sid scroll_ narrowcast
4 5 to text_size +4
text_size text
1-253 Extended ASCII
3.3.33 CHANNEL_REF_REQ
BYTE 0 1 FIELD CHANNEL_TABLE_REQ start_channel_number 0x2D 1 - 225 VALUE DESCRIPTION Channel Table Request header. DSP returns the channel reference table (CRT) segment from start_channel_number to start_channel_number + 30.
BYTE 0 1 2 - 255
FIELD CHANNEL_TABLE_CFM channel_number channel_ref_table 0xAD 1 - 225
VALUE
DESCRIPTION Channel Table Confirm header Starting channel number. Channel Reference Table Reference: Service Layer Specification.
3.3.34 ARTSNGCHG_LIST_REQ
BYTE 0 FIELD ARTSNGCHG_LIST_REQ 0x2E VALUE DESCRIPTION Artist/Song Change List Request Header
BYTE 0 1
FIELD ARTSNG_LIST_CFM channel_bit_mask00 0xAE bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 -
VALUE
DESCRIPTION Artist/Song List Confirm Header
channel 007 channel 006 channel 005 channel 004 channel 003 channel 002 channel 001 channel 000
Channel mask 0 - artist/song status indication for channels from 0 to 7.
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2 channel_bit_mask01 bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - ...... ...... ...... bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - channel 255 channel 254 channel 253 channel 252 channel 251 channel 250 channel 249 channel 248 channel 015 channel 014 channel 013 channel 012 channel 011 channel 010 channel 009 channel 008 Channel mask 1 - artist/song status indication for channels from 8 to 15.
...... ...... ...... 32
...... ...... ...... channel_bit_mask31
....... ....... ....... Channel mask 1 - artist/song status indication for channels from 248 to 255.
3.3.35 PROGTYPE_LIST_REQ
BYTE 0 1 FIELD PROGTYPE_LIST_REQ REQ TYPE 0x2F 0x01 - program types availables on lineup 0x02 - program types selectable by the user FIELD PROGTYPE _LIST_CFM CMD_RESPONSE 0xAF 0x01 - command succesfull 0xFF - command fails 1 progtype_bit_mask00 bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - program program program program program program program program program program program program program program program program type type type type type type type type type type type type type type type type 07 06 05 04 03 02 01 00 23 22 21 20 19 18 17 16 VALUE DESCRIPTION Program Type List Confirm header The command can fails in case that the command byte 1 is wrong (a non implemented number) Program type mask 0 - program type status indication bits for program type 0 to program type 7. VALUE DESCRIPTION Program Type List Request
BYTE 0 1
2
progtype_bit_mask01
Program type mask 1 - program type status indication bits for program type 8 to program type 15.
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3 progtype_bit_mask02 bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - bit 7 - bit 6 - bit 5 - bit 4 - bit 3 - bit 2 - bit 1 - bit 0 - program program program program program program program program program program program program program program program program type type type type type type type type type type type type type type type type 15 14 13 12 11 10 09 08 31 30 29 28 27 26 25 24 Program type mask 2 - program type status indication bits for program type 16 to program type 23.
4
progtype_bit_mask03
Program type mask 3 - program type status indication bits for program type 24 to program type 31.
3.3.36 HWID_READ_REQ
BYTE 0 FIELD HWID_READ_REQ 0x31 VALUE DESCRIPTION HWID Read Request header
BYTE 0 1-8
FIELD HWID_READ_CFM Hwid 0xB1
VALUE
DESCRIPTION HWID Read Confirm header Hardware Identification (HWID).
Alphanumeric characters
3.3.37 UTC_REQ
BYTE 0 FIELD UTDC_REQ 0x32 VALUE DESCRIPTION HWID Read Confirm header
BYTE 0 1
FIELD UNIVERSAL_TIME_CFM utc_status 0xB2
VALUE
DESCRIPTION Universal Time Confirm header If UTC was not received, then DSP returns UTC_ABSENT. If UTC was received, then DSP returns UTC_PRESENT. Universal Time. Reference: Transport Layer. Master Frame Counter Reference: Transport Layer Specification.
0x00 - UTC_ABSENT 0x01 - UTC_PRESENT
2-8 9 - 11
UTC MFC
3.3.38 CLEAR_DATA_REQ
BYTE 0 FIELD CLEAR_DATA_REQ 0x34 VALUE DESCRIPTION Clear Data Request
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1 data_to_clear 0x01 - channel reference user data to clear table 0x02 - program label 0x04 - SIB 1 0x08 - SIB2 0x10 - Last channels selected 0x1F- all sections (except last channels selected) BYTE 0 1 FIELD CLEAR_DATA_CFM CMD RESULT 0xB4 0x01 - cmd succesfull 0xFF - cmd fails VALUE DESCRIPTION Clear Data Confirm Command result. This command can fails because the byte 1 in the command buffer has a wrong number
3.3.39 PROGLABEL_LIST_REQ
BYTE 0 BYTE 0 1-2 size FIELD PROGLABEL_LIST_REQ FIELD PROGLABEL_LIST _CFM 0xB6 0x0000 - 0xFFFF 0x36 VALUE VALUE DESCRIPTION Program Label List Request DESCRIPTION Program Label List Confirm header. Size of the Program Label List Confirm response. MSB in byte 1. LSB in byte 2. The first available program type. program label. ...... ...... ...... The last available program type. program label.
3 4 - 19 ...... ...... ...... size 17 size 16 to size (1-2)
program_type program_label ...... ...... ...... program_type program_label
1 - 31 ISO-8859-1 character set. ...... ...... ...... 1 - 31 ISO-8859-1 character set.
3.3.40 BIC_LABEL_REQ
BYTE 0 1 location FIELD BIC_LABEL_REQ 0x37 0x00 - AUDIO 0x01 - DATA 0x00 - no request 0x01 - get artist label 0x00 - no request 0x01 - get song label VALUE DESCRIPTION BIC Label Request Since SDEC can extract two services simultaneously, XM stack assigns an extraction location. If the system controller is requesting the extended BIC artist label, then set this flag to 0x01. If the system controller is requesting the extended BIC song label, then set this flag to 0x01.
2
extartist_label_flag
3
extsong_label_flag
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4 text_label_flag 0x00 - no request 0x01 - get BIC text If the system controller is requesting the BIC text label, then set this flag to 0x01. RECOMMENDATION: It's strongly recommended that the system controller set the text_label_flag to 0x00. For BIC text, its recommended system controller use BIC_TEXT_REQUEST command. BYTE 0 1 2 FIELD BIC_LABEL_CFM command_status location 0xB7 0x01 - SUCCESFUL 0xFF - FAILURE 0x00 - location 0 0x01- location 1 1 - 255 0x00 - ABSENT 0x01 - PRESENT VALUE DESCRIPTION BIC Label Confirm header. Command status Since SDEC can extract two services simultaneously, XM stack assigns an extraction location SID of extracted location. artist label present or absent from response. Please note this octet is only present when the extartist_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command. artist label size Please note this byte is only present when the extartist_label_flag is set to 0x01 (PRESENT). in BIC_LABEL_REQ command. artist name Please note this byte is only present when the extartist_label_flag is set to 0x01 (PRESENT).in BIC_LABEL_REQ command Note: The maximum size of the BIC extended artist name is 80 bytes. Therefore artist_size < = 80 bytes. song label present or absent from response Please note this octet is only present when the extsong_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command. song label size. Please note this byte is only present when the extsong_label_flag is set to 0x01 (PRESENT).in BIC_LABEL_REQ command.
3 4
sid extartist_flag
5 to 6
extartist_size
1 to 80
7 to (6+exartist_size)
extartist_label
ISO-8859-1 character set
artist_size +8
extsong_flag
0x00 - ABSENT 0x01 - PRESENT
artist_size + 9 to artist_size +10
extsong_size
1 - 80
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artist_size + 11 to artist_size +10 extsong label ISO-8859-1 character set song label Please note this byte is only present when the extsong_label_flag is set to 0x01 (PRESENT) (PRESENT).in BIC_LABEL_REQ command Note: The maximum size of the BIC extended song title is 80 bytes. Therefore song_size < = 80 bytes. If BIC text was not received, then DSP returns ABSENT. If BIC text was received, then DSP returns PRESENT.Please note this octet is only present when the text_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command text size. Please note this byte is only present when the text_label_flag is set to 0x01 (PRESENT). in BIC_LABEL_REQ command SID of extracted location. Please note this byte is only present when the text_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command Scrolling and narrowcast information. Please note this octet is only present when the text_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command. Reference: Service Layer Specification; Revision 1.4; Section 8.11 size of the text message Please note this octet is only present when the text_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command. BIC Text. Please note this octet is only present when the text_label_flag is set to 0x01 (PRESENT) in BIC_LABEL_REQ command. Reference: Service Layer Specification; Revision 1.4; Section 8.11
artist_size +song_size + 12
bic_text_status
0x00 - ABSENT 0x01 - PRESENT
artist_size + 13 to artist_size + 14
text_size
1 - 253
artist_size + 15
sid
1 - 255
artist_size + song_size +16
scroll_narrowcast
see specification
artist_size + song_size +17
text_size
1-253
artist_size + song_size +18 to artist_size + song_size + text_size + 17
scroll_narrowcast
see specification
3.3.41 DISPLAY_MASK_REQ
BYTE 0 1 2 3 4 FIELD DISPLAY_MASK_REQ service_label artist_label song_label program_label 0x4C 8, 10, 16 8, 10, 16 8, 10, 16 8, 10, 16 VALUE DESCRIPTION Display Mask Request service label display mask artist label display mask song label display mask program label display mask
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3.3.42 SDEC_VER_REQ
BYTE 0 1 FIELD SDEC_VER_REQ sdec_version 0x4D 0x21 HCMOS 7 0x25 HCMOS 8 VALUE DESCRIPTION Read Data Request SDEC version number expected by system controller.
3.3.43 FAST_CLEAR_EVENT
BYTE 0 1 2 FIELD FAST_EVENT_CLR_REQ Reg mask 0x50 0x45 - 0x48 0x4B - 0x4C VALUE DESCRIPTION Event or error bit/s clear request Event or Error register to be written Mask to apply to the specified register (e.g. 0x01 clear bit 1 of the specified register)
3.3.44 FAST_DISABLE_INT_REQ
BYTE 0 1 2 FIELD FAST_DISABLE_INT_REQ Reg mask 0x51 0x41 - 0x44 0x49 - 0x4A VALUE DESCRIPTION Event or error interrupt/s disable request Event and Error enable interrupt register to be written Mask to apply to the specified register (e.g. 0x01 clear bit 1 of the specified register)
3.3.45 FAST_ENABLE_INT_REQ
BYTE 0 1 2 FIELD FAST_ENABLE_INT_REQ Reg Mask 0x52 0x41 - 0x44 0x49 - 0x4A VALUE DESCRIPTION Event or error interrupt/s enable request Event and Error enable interrupt register to be written Mask to apply to the specified register (e.g. 0x01 set bit 1 of the specified register)
3.3.46 FAST_EXTRACT_REQ
BYTE 0 1 FIELD FAST_EXTRACT_REQ Location 0x53 0x00 - location 0 0x01 - location 1 VALUE DESCRIPTION Fast Extract Request header Since DSP can extract two services simultaneously, XM stack assigns an extraction location.
2
channel_or_sid_flag
0x00 - use channel number If channel number is used, then the SDEC given in byte 3. will get the SID and PCIDs from CRW. 0x01 - use SID given in byte 4
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3 4 5 channel_number Sid Extract_type 1 - 255 1 - 255 0x03 AMBE 0x05 AAC 0x0A Trans_data 5 - 254 channel number Service Identifier Service Component Type to extract.
6
primary_pcid
Primary Payload Channel Identification. SDEC will check the PCID given by the system controller is still the same as the one in CRW, If different, then the extraction fails and SDEC sets the FAST_EXTRACTION_COMPLETEDx event bit. Reference: Transport Layer Specification; Revision 1.2; page 40 Secondary Payload Channel Identification SDEC will check the PCID given by the system controller is still the same as the one in CRW, If different, then the extraction fails and SDEC sets the FAST_EXTRACTION_COMPLETEDx event bit. Reference: Transport Layer Specification; Revision 1.2; page 40 Routing information A data service component can only be routed to the data port (DAT_PORT). An audio service component is routed to audio port (AUD_PORT), data port (DAT_PORT) or both the audio and data port (BOTH_PORT).
7
secondary_pcid
5 - 254
8
Routing
0x00 - No routing 0x01 - AUD_PORT 0x02 - DAT_PORT 0x03 - BOTH_PORT
4.0 I/O CELLS DESCRIPTION) Input Pad Buffer
A Z
EXTERNAL PIN A
INPUT CAP. 1.3pF
D98AU906
2) Input Pad Buffer with Active Pull-up
50K A Z
EXTERNAL PIN A
D98AU907A
INPUT CAP. 1.3pF
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3) Schmitt Trigger Input Pad Buffer
A Z
EXTERNAL PIN A
INPUT CAP. 1.3pF
D99AU1072
4) Output Pad Buffer, 4mA with slew rate control.
EXTERNAL PIN
A Z
D98AU920
MAX LOAD 100pF
A
5) BiDir Pad Buffer, 4mA with slew rate control.
EN IO A
EXTERNAL PIN I/O
INPUT CAP. 1.3pF
MAX LOAD 100pF
ZI
D99AU1074A
6) Schmitt Trigger BiDir Pad Buffer, 4mA with slew rate control.
EN IO A
EXTERNAL PIN I/O
INPUT CAP. 1.3pF
MAX LOAD 100pF
ZI
D98AU921
7) Analog Pad Buffer
I/O A 550 Z
EXTERNAL PIN A
INPUT CAP. 1.9pF
STA400_1
5.0 TIMING DIAGRAM (GUARANTED BY DESIGN) 5.1 Audio DAC Interface (PCM)
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a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (output) tr SDO tsdo SCKT tsckt LRCKT tlrckt tf
Notations: Cload_XXX is the load in pF on the XXX output. pad_timing(Cload_XXX) is the propagation delay added to the XXX pad due to the load. The following table gives this timing .
Load (pF) 25 50 75 100 max pad_timing (rise) 6 ns 10 ns 12 ns 14 ns max pad_timing (fall) 10.6 ns 13 ns 15.4 ns 18 ns
tsdo_max = 3.5 + pad_timing(Cload_SDO) - pad_timing(Cload_OCLK) tsckt_max = 4.0 + pad_timing(Cload_SCKT) - pad_timing(Cload_OCLK) tlrckt_max = 3.5 + pad_timing(Cload_LRCKT) - pad_timing(Cload_OCLK) The Tr and Tf depends on the load on the different pads but at a given load, the Tr and Tf timings are identical for OCLK(output case), SCKT, LRCKT, SDO.
b) OCLK in input
OCLK (input) tr SDO
tlo thi tf
tsdo SCKT tsckt LRCKT tlrckt toclk
Thi min = 5 ns Tlo min = 5 ns Toclk min = 25 ns tsdo_max = 5.5 + pad_timing(Cload_SDO) ns
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tsckt_max = 6.0 + pad_timing(Cload_SCKT) ns tlrckt_max = 5.5 + pad_timing(Cload_LRCKT) ns tr max = 20 ns tf max = 20 ns 5.2 RESET_N The Reset_N min duration (t_reset_low_min) is 10 us. The RESET_N is active low.
RESET_N tf
t_reset_low_min tr
5.3 CLK_IN The CLK_IN typical frequency is 23.92 Mhz. The min high and low time are 5 ns. Trise_clkin max = 16 ns Tfall_clkin max = 16 ns
t_clkin_low_min CLK_IN t_clkin_high_min tf tr
5.4 Single bit inputs : PCFS, PLL_SYNC The min pulse duration (high or low) on these inputs is 20 ns. Trise max = 20 ns Tfall max = 20 ns
interrupt sent to DSP core
Internal DSP clock FIT_*, IT_*
at least 1 DSP clk period
PCFS, PLL_SYNC tr
t_high_min
tf
5.5 Single bit outputs : I958_OUT, EVENT_IRQ(GPIO_0), INT1(GPIO_1), INT2(GPIO_2),
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CAP_RST(GPIO_4)
Load (pF) 25 50 75 100 max pad_timing (rise) 6 ns 10 ns 12 ns 14 ns max pad_timing (fall) 10.6 ns 13 ns 15.4 ns 18 ns
I958_OUT, EVENT_IRQ(GPIO_0), INT1(GPIO_1), INT2(GPIO_2), CAP_RST(GPIO_4)
tf
tr
PC bitstream interface : USSIO interface in input (PCDC, PCSD)
PCDC
tpcdc_min_hi
t_pcdc_min_low tpcdc_min_period
PCDC PCSD tpcsd_setup tpcsd_hold
tpcsd_setup_min = 15 ns tpcsd_hold_min = 15 ns tpcdc_min_hi = 20 ns tpcdc_min_low = 20 ns tpcdc_min_period = 60 ns tr_max = 20 ns tf_max = 20 ns 5.6 USSIO in output : Data Port output (DP_EN, DP_DATA, DP_CLK)
DP_CLK tr DP_DATA t_dpdata DP_EN t_dpen
Notations: Cload_XXX is the load in pF on the XXX output. pad_timing(Cload_XXX) is the propagation delay added to the XXX pad due to the load. The following table gives this timing. t_dpen_max = 6.0 + pad_timing(Cload_DP_EN) - pad_timing(Cload_DP_CLK)
tf
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Load (pF) 25 50 75 100 max pad_timing (rise) 6 ns 10 ns 12 ns 14 ns max pad_timing (fall) 10.6 ns 13 ns 15.4 ns 18 ns
t_dpdata_max = 6.0 + pad_timing(Cload_DP_DATA) - pad_timing(Cload_DP_CLK) The Tr and Tf depends on the load on the different pads but at a given load, the Tr and Tf timings are identical for DP_CLK, DP_DATA, DP_EN. DP_DATA and DP_EN must be sampled on the falling edge of DP_CLK.
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DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.22 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.32 1.45 0.38 0.20 16.00 14.00 12.35 0.65 16.00 14.00 12.35 0.60 1.00 0.75 0.018 0.002 0.053 0.009 0.003 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.013 0.057 0.015 0.008 0.630 0.551 0.295 0.0256 0.630 0.551 0.486 0.024 0.0393 3.5(min.), 7(max.) 0.030
OUTLINE AND MECHANICAL DATA
TQFP80 (14x14x1.40mm)
D D1 D3
A A2
A1
60 61 41 40
0.10mm .004 Seating Plane
e
E3 B
E1
E
PIN 1 IDENTIFICATION
Gage plane 0.25mm
80 1 20
21
K
TQFP80L
C L L1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved
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